GaN HEMT power transistors have become an attractive option for high switching frequency converters in the 600 - 650 V breakdown voltage range. The high voltage and current variation rates involved in the commutation process of such devices in combination with the package terminals stray inductance introduce unwanted and dangerous over-voltages and oscillations. For this reason TO-247 or TO-220 packages typically used in the medium power range (for example for IGBTs and Super Junction MOSFETs) are avoided for discrete GaN HEMTs, which are mainly packaged in different surface mount (SMD) formats. In SMD packages, the stray inductances are in the range of the nH and below, but the heat extraction plane (typically a Cu thermal pad) is often at the same level than the electrical terminals, hindering the simultaneous optimum design of the electrical and thermal circuit layouts. This work analyses the high speed switching (i.e., optimum circuit layout) versus thermal management (i.e., low thermal resistanece) trade-off, comparing different options for cooling p-GaN HEMT transistors in a PG-DSO SMD package. Two approaches based only on natural convection have been considered: board-level and heatsink-based solutions. Comparison among the different cooling options has been quantified by means of the HEMT junction to ambient thermal impedance, evaluated with the devices assembled in test-vehicle PCB boards. The results provide information for practicing engineers who would like to have a point of reference for passive cooling solutions of discrete GaN HEMTs.

In this work, the Infrared Lock-in Thermography (IR-LIT) is reported as a powerful tool for power devices diagnosis. They are monitored by thermal means after being biased in the frequency domain to activate and locate the weak spots responsible for their misbehaviour. As case studies, three different power devices are analysed: i) a Vertical Double Diffused MOS (VDMOS) presenting an elevated gate leakage current; ii) a SiC Schottky Barrier Diode with Tungsten contact (W-SBD) featuring a Schottky barrier modification by metal contact change; and iii) a Rad-Hard V-JFET with a lower breakdown voltage and a higher gate leakage current than expected.

This paper presents a method for computing the total semiconductor power losses within different bidirectional switches aimed to build AC/AC converters (matrix converters). Bidirectional switches built with different power device technologies are characterized in static as well as in dynamic operation in order to extract their key parameters and thus, model their behavior in the conduction and switching mode. This characterization data allows computing accurately total bidirectional switches power dissipation (conduction and switching power losses) and comparing the power losses associated to different power device technologies. The proposed numerical modelling tool will allow the converter designer to choose the optimum power semiconductors in terms of efficiency and cost.

In this work, Lock-in Infrared Thermography (LIT) is presented as a powerful tool for failure analysis in power devices. These devices are electrically characterized in the frequency domain by thermal means to activate weak spots responsible for their misbehavior. As case studies, two different power devices are inspected using the LIT technique: a Vertical Double Diffused MOS (VDMOS) presenting an elevated gate leakage current and a SiC Schottky Barrier Diode with Tungsten contact (W-SBD) presenting a Schottky barrier modification by metal contact change.

The numerous limitations of Electro Mechanical Relays (EMRs) for implementing Single-Pole, Single-Throw (SPST) Bi-Directional Switches (BDS) lead to new developments based on power semiconductor devices. This work gives an insight into the design and operation of BDSs based on the combination of unidirectional voltage blocking and bidirectional current conduction power devices, which aim to substitute EMRs in home appliances. The developed BDSs are fully characterized.