In this work, the feasibility of Si ion-implantation channel engineering in metastable α-Ga2O3 is directly compared with the well-established implantation process used in β-Ga2O3 lateral MESFETs. Identical multi-energy Si implantation schemes (10-175 keV) and thermal annealing conditions were applied to both polymorphs in order to evaluate the compatibility of implantation-based doping with the thermal stability window of α-Ga2O3. For β-Ga2O3, Si implantation followed by high-temperature annealing (900–1100 °C) successfully enabled conductive channel and ohmic contact formation, leading to functional lateral MESFET operation with proper current modulation and saturation behaviour. In contrast, α-Ga2O3 layers grown on m-plane sapphire exhibited a strong limitation associated with their metastable nature. An ALD-deposited Al2O3 capping layer delayed the α→β phase transition up to approximately 700 °C, as confirmed by X-ray diffraction analysis. However, electrical measurements revealed no measurable channel conduction after annealing within this temperature range, indicating insufficient thermal activation of implanted Si donors. At higher annealing temperatures, where dopant activation would normally be expected, the α-phase underwent complete reconstructive transformation into β-Ga2O3, accompanied by severe structural degradation and suppressed electrical transport. These results demonstrate that the thermal budget required for conventional implantation-based donor activation exceeds the metastability window of α-Ga2O3, even when thermal stabilization layers are employed. The study therefore identifies a fundamental technological limitation for ion-implantation-defined α-Ga2O3 power devices and highlights the need for alternative low-thermal-budget doping and device fabrication strategies.

Die-level electrical stress caused by current crowding is investigated in Insulated Gate Bipolar Transistors outside zero-voltage switching operation. This stress occurs during the turn-on phase of an induction cooking resonant inverter, where the switching frequency sweeps from 150 to 50 kHz. The stress is monitored on a sub-100 mu s timescale with a 10 mu m lateral resolution using an infrared (IR) thermographic setup. To improve signal-to-noise ratio and time resolution, a Fourier-based time reconstruction strategy is applied. Electrothermal SPICE simulations complement the interpretation of measurements, providing insights into current crowding under such stressful operating conditions. The analysis under soft-start conditions reveals two key findings. First, heat dissipation, and consequently current conduction, present a time-dependent two-dimensional distribution, with hotspots forming in low-impedance regions detectable via IR thermography. Second, in this nonhomogeneous current distribution, the SPICE electrothermal model predicts the most frequently occurring value of the temperature distribution (statistical mode) across the active area more accurately than the mean value. This observation may establish a link to the concept of junction temperature, which is traditionally derived using thermo-sensitive electrical parameters.

Chip embedding power modules are a promising solution for multilevel converter implementation due to their high level of integration, thermal performance, and low parasitic inductance compared with standard power modules. This study employs COMSOL's Magnetic Fields Only Currents (MFCO) interface to evaluate partial inductance in power chip embedding boards, focusing on 3D modelling of a complex geometry, mesh refinement, and some issues arising from the definition of boundary conditions. A practical case is presented to illustrate these phenomena. Finally, an experimental measurement is also shown to validate the simulation results.

For the first time, the Internal InfraRed-Laser Deflection (IIR-LD) method is applied to successfully measure the carrier density profile in a 1.2 kV SiC Schottky diode under overcurrent. This overstress induces high-level injection into the drift region at the junction termination extension (PiN diode activation). Novel strategies compensate for key issues in IIR-LD data; i.e., decoupling temperature and carrier density, and correcting for the effect of the beam's larger diameter (similar to 16 mu m) relative to the inspected layer (13 mu m thick). In the drift region, experimental results match simulations, showing carrier densities ranging from 2.73x10(16) to 3.47x101(6) cm(-3). Moreover, substrate data reveal temperature-driven dopant ionization.

For the first time, die-level electrical stress from current crowding is analyzed by InfraRed (IR) thermography in an IGBT operating in a half-bridge resonant converter outside the zero-voltage switching (ZVS) regime from 150 to 75 kHz. Custom IR image processing with Fourier coefficients and time reconstruction enables non-invasive 10 pm, submillisecond monitoring of the device's surface thermal map during switching operation, identifying overheated areas in low-impedance regions at a tens of microseconds time scale.

This work presents the integration of a smart switching-cell for multilevel converters, utilizing chip embedding technology and 750V, 12mSI SiC power MOSFETs. The switching-cell design was optimized in terms of partial inductance and thermal resistance. Simulation results align closely with experimental data, showing a thermal resistance junction to backside of 0.63 K/W and a parasitic inductance of 2.7nH at 10MHz. The electrical performance and functionality of the switching-cell is also experimentally validated, confirming the interest of chip embedding for smart power modules integration in the medium voltage/power range.

The junction temperature of power semiconductor devices is a key parameter to consider when designing power systems to assure proper operation and reliability. In this paper, a non-intrusive method based on a fast clamping circuit and a look-up table is proposed to utilize the ON-state voltage as a temperature sensitive electrical parameter (TSEP). It allows junction temperature monitoring of Si and SiC MOSFETs during converter operation, achieving steady-state temperature deviations below 1 degrees C.

Chip embedding is emerging as a promising advanced packaging technology, offering significant advantages over conventional methods in performance, reliability and miniaturization. This work focuses on the topside and backside die -level interconnection techniques needed for enabling chipembedding implementation. A novel in-house technique is presented to selectively re -metallize with Cu the contact pads of any device by hard shadow masking, to allow subsequent micro via standard PCB contact process. In this work the technique is used to re-metallize the gate and source pads of 750V-12m Omega SiC MOSFET dies, which are then attached to Cu leadframes with a robust Ag sinter paste. These assemblies have been successfully embedded for implementing elementary switchingcells used in multilevel power converters designed for electric traction applications.

A robust methodology is proposed for determining and assessing measurement uncertainties in thermal imaging systems when the Fourier coefficient-based time-reconstructed method is used. This comprehensive approach addresses factors such as camera-induced noise, setup-related errors, and data postprocessing strategies. As a case study, this methodology is applied to measure a thermal test chip (TTC) using a thermo-reflectance (TR) setup. The results are validated with the stroboscopic boxcar averaging technique. This study yields valuable insights. The camera introduces a Rayleigh-distributed white noise, which is extracted in both postprocessing methods. Image registration mitigates thermo-mechanical displacements during calibration effectively. Key uncertainties are identified for each method. Registration and calibration errors remain under 5%, with camera noise contributing only 0.5 degrees C of measurement uncertainty. These uncertainties allow for accurate thermal measurements with a precision of 2 degrees C and preserving a high spatial resolution ( similar to 1 mu m).

To expedite testing, time-dependent dielectric breakdown (TDDB) analyses are conducted on commercial 4H-SiC MOSFETs at high gate-to-source voltages (VGS), under Fowler-Nordheim conduction only. However, as inferred, such conditions induce impact ionization-generated holes in the dielectric layer (SiO2), resulting in a state transition in the effective dipolar moment. This accelerates the SiO2 degradation leading to an overestimation of its intrinsic lifetime at typical VGS values for gate driving in power converters. To address this, a physics-based approach is proposed to design TDDB tests under such conditions and to correct the intrinsic lifetime prediction at nominal VGS values, shortening the testing time by up to two orders of magnitude. Thus, the proposed method is a well-suited candidate to be considered in SiC power device qualification standards, still under development.

A novel solution for off-chip electrothermal studies in power devices at die level and short timescales is reported. The proposed method involves acquiring a sequence of thermal images on the top of the die with an infrared (IR) camera, while the device is biased under a periodic nonharmonic modulated current. Fourier coefficients are then extracted using lock-in strategies, and the time evolution of the device thermal map is reconstructed using Fourier series. To evaluate and showcase its potential, the conventional approach of boxcar averaging is implemented and used as a reference. As a case study, a reverse-conducting insulated gate bipolar transistor (RC-IGBT) is thermally measured under both forward and reverse modes. The proposed strategy significantly improves the thermal and time resolution, overcoming the limitations of the camera’s frame rate and noise resolution. Moreover, the impact of current crowding on the power device is studied at the millisecond timescale, considering both biasing modes.

In this work a Finite Element Simulation thermal and mechanical study of a power SOT-227 package with a diamond die is performed in order to assess the impact of its mechanical properties when compared to the standard silicon dies. Furthermore, the simulations are carried using silver sintering as die-attach material, and different conditions and parameters that affect its mechanical behaviour are explained and quantified in order to illustrate the variation in results and the need for reliable modelisation and material parameters identification. Mechanical behavioural data is also extracted for the sintered silver simulating a lap shear test, which is used to validate a non-linear identification method of the Anand model parameters. The results show that the inclusion of a diamond die increases significantly the amount of stress and plastic deformation in the die-attach layer, which will lead to reliability problems and shorter life cycle. In addition, when using silver sintering as die-attach, the model parameters should be extracted for each particular material, owing to the fact that the mechanical properties of the die-attach layer strongly depend on its processing conditions. Finally, the Anand model parameter identification routine was validated, obtaining minimum deviation from the original values used to simulate the pseudo-experimental data.

Die-level current crowding phenomena are analyzed at the microsecond timescale with an internal IR-Laser Deflection set-up. To this end, the 4H-SiC plasma-optical coefficient for the refractive index is reported for the first time. A SiC Schottky diode with an edge termination based on a junction termination extension is used as a test vehicle. Under biasing conditions, the edge termination starts a local bipolar conduction along the device active area perimeter, leading to current crowding effects. Using refractive index measurements, a depth-resolved carrier profile is extracted and assessed using both, simulation and Free Carrier Absorption measurements.

In this work, an improved self-powered gate driver power supply is proposed, analyzed by simulation and experimentally validated. This solution is based on the addition of a voltage regulator and it achieves a floating, constant and robust voltage to supply the gate driver and auxiliary circuits (protections, sensors, local control and communications) in switching cells for multilevel converters implementation. The obtained gate driver supply voltage is stable for a wide range of frequencies and auxiliary circuit current consumptions. Moreover, the main characteristics of the main transistor turn-on and turn-off are preserved while decreasing the power dissipation of the gate driver power supply circuit.

Current Crowding phenomenon is one of the most important issues compromising power device reliability. In this work a 4-H SiC Schottky diode with a junction termination extension is studied when this phenomenon occurs. TCAD modelling of the device is detailed and different doping profiles for the n-type buffer layer of the drift zone are simulated. The obtained results are assessed with experimental measurements using the Internal Infrared Laser Deflection and Free-Carrier Absorption techniques. It is highlighted that the incomplete ionization modulates the carrier concentration in the device drift layer and, consequently, it may have a certain role in this process.

The thermal resistance of a high electron mobility transistor (HEMT) forming part of a monolithic microwave integrated circuit (MMIC) is noninvasively extracted under real working conditions (electrical and thermal) by infrared thermal imaging. The HEMT thermal resistance considers the device local maximum temperature and dissipated power. An experimental approach to this end is currently not available, as the HEMTs thermal interaction does not allow extracting its individual heat generation. Thanks to thermal field confinement offered by heat source frequency modulation, the power dissipation in each device is inferred, making feasible its individual thermal resistance extraction. As a result, reasonable values of the local thermal resistance of each individual HEMT integrated in the MMIC (i.e., 57.8 ± 3.4 °C/W and 24.8 ± 1.4 °C/W) are obtained in agreement with studies on discrete devices available in the literature.

The large electrocaloric coupling in PbZrO3 allows using high-speed infrared imaging to visualize antiferroelectric switching dynamics via the associated temperature change. We find that in ceramic samples of homogeneous temperature and thickness, switching is nucleation-limited and fast, with devices responding in the milisecond range. By introducing gradients of thickness, however, it is possible to change the dynamics from nucleation-limited to propagation-limited, whereby a single phase boundary sweeps across the sample like a cold front, at a speed of c.a. 20 cm/s. Additionally, introducing thermostatic temperature differences between two sides of the sample enables the simultaneous generation of a negative electrocaloric effect on one side and a positive one on the other, yielding a Janus-like electrocaloric response.

We have studied the electrocaloric response of the archetypal antiferroelectric PbZrO3 as a function of voltage and temperature in the vicinity of its antiferroelectric-paraelectric phase transition. Large electrocaloric effects of opposite signs, ranging from an electro-cooling of -3.5 K to an electro-heating of +5.5 K, were directly measured with an infrared camera. We show by calorimetric and electromechanical measurements that the large negative electrocaloric effect comes from an endothermic antiferroelectric-ferroelectric switching, in contrast to dipole destabilization of the antiparallel lattice, previously proposed as an explanation for the negative electrocaloric effect of antiferroelectrics.

A determination of the Anand viscoplastic model parameters for 88Au12Ge solder alloy is presented in this work. Using experimental data from temperature and rate dependent shear stress tests, the nine characteristic parameters for the aforementioned model were obtained through non-linear fitting using a Least Squared Residual approach. The calculated estimated parameters were used to replicate the conditions of the experimental shear test using Finite Element Simulations in order to validate the final model obtained. Results show a fitting temperature dependency with understress at lower temperatures and a tendency to overstress at higher temperatures. The obtained model response shows no rate dependent behaviour (probably as a result of the small dataset used) and the non-ideal Anand distribution of saturation stresses of the experimental data. Nervetheless, the proposed approach provides a parameter dataset useful for FEA thermos-mechanical simulation of die-attach layers in power modules.

A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metal-oxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PA's output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.