We propose complete technology-design-system cooptimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R wire ) multiplied by logic gate input pin cap (C pin ), R wire ×C pin , is identified as a major limiter of performance and power at N7. Reducing C pin is crucial to mitigate abruptly rising BEOL R wire effect. Depopulation of fin is one of most effective methods to reduce C pin , and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C pin , whose benefit is enhanced by reduction of other C pin components. Careful choice of routing metal stack ameliorates adverse effect of R wire . Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P fin ) is needed to reduce transistor resistance (R tr ). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2x peak data rates vs 28nm, and 2x carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving similar to 2x gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.