Modern mobile devices have retained the same integration and memory architecture for the past decade, bounded by complex fabrication processes and tight thermal/power constraints. As large language models (LLMs) grow in popularity, the typical LPDDR-backed package-on-package integration is showing major limitations in performance scaling. We survey modern mobile device specifications and report on trends addressing AI performance. We then model emerging memory standards–LPDDR6, LPW, and LLW–in system and circuit simulators to extract performance and energy trends on 1B, 3B, and 8B parameter LLMs. We find that emerging standards backed by vertical post stacks offer over 4x performance and 2x IO energy improvement over LPDDR5 baseline. 2.5D integration with LLW further pushes performance and energy beyond 5x improvement. Finally, we extrapolate performance for different pin counts and data rates, showing that bridging the compute-bandwidth gap by an order of magnitude (20x current performance) remains off-target.

High-performance edge artificial intelligence (Edge-AI) inference applications aim for high energy efficiency, memory density, and small form factor, requiring a design-space exploration across the whole stack-workloads, architecture, mapping, and co-optimization with emerging technology. In this article, we present a system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enabled technology offerings. The framework is built on three engines that provide the physical design characterization, dataflow mapping optimizer, and system efficiency predictor. The framework builds on a systolic array accelerator to provide the design-technology characterization points using advanced imec A10 nanosheet CMOS node along with emerging, high-density voltage-gated spin-orbit torque (VGSOT) magnetic memories (MRAM), combined with memory-on-logic fine-pitch 3-D wafer-to-wafer hybrid bonding. We observe that the 3-D system integration of static random-access memory (SRAM)-based design leads to 9% power savings with 53% footprint reduction at iso-frequency with respect to 2-D implementation for the same memory capacity. Three-dimensional nonvolatile memory (NVM)-VGSOT allows 4x memory capacity increase with 30% footprint reduction at iso-power compared with 2-D SRAM 1x . Our exploration with two diverse workloads-image resolution enhancement (FSRCNN) and eye tracking (EDSNet)-shows that more resources allow better workload mapping possibilities, which are able to compensate peak system energy efficiency degradation on high memory capacity cases. We show that a 25% peak efficiency reduction on a 32x memory capacity can lead to a 7.4x faster execution with 5.7x higher effective TOPS/W than the 1x memory capacity case on the same technology.

A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from the supply voltage to the standard-cells for a power delivery network design in a 3 nm logic node. The simulated PDN elicited high EM-tolerance. Despite EM voiding in multiple PDN segments, the EM induced IR-drop increase at the standard-cell level stayed below 3.3% without any catastrophic standard-cell failures. Use of ruthenium rails reduced IR-drop penalty of system EM by a factor of ~0.6 compared with copper rails.

Electromigration has been a major reliability concern for nano-interconnects in CMOS applications. With further CMOS miniaturization, the cross-sectional area of nano-interconnects is further scaled resulting in a significant increase of current densities. It has been shown that $j_{max}$ of copper interconnects degrades abruptly at scaled linewidths, predicting increased susceptibility to electromigration. Nevertheless, there is still a dilemma given that the electromigration metrics are typically obtained from electromigration tests on single isolated interconnects and may not be readily translated into metrics for interconnect networks of CMOS designs, which is key for enabling realistic reliability predictions at system-level. In this paper, we demonstrate a physics-based system-level electromigration modelling platform aiming to address the shortcomings of the standard of practice for electromigration compliance checks during the design phase and enhance the accuracy of lifetime predictions from a system viewpoint. The framework is specifically applied to the case of PDN for a 3 nm technology node.

System scaling enabled by Moore's scaling is increasingly challenged by the scarcity of resources such as power and interconnect bandwidth. This has become more challenging under the requirements of seamless interaction between big data and instant data (Figure MM-1). Instant data generation requires ultra-low-power devices with an “always-on” feature at the same time with high-performance devices that can generate the data instantly. Big data requires abundant computing, communication bandwidth, and memory resources to generate the service and information that clients need.

ABSTRACTWe are living in a connected world with access to data in vast amounts. This connectivity is enhanced by more intelligent sensors and human-computer interfaces bringing people closer to computation in a more natural and accessible way. Instant data generation requires ultra-low-power devices with an "always-on" feature at the same time with high-performance devices that can generate the data instantly. Big data requires abundant computing, communication bandwidth, and memory resources to generate services and sensible information that people need. But transfer of data becomes a limitation for the scaling of systems where both on-chip and off-chip interconnects become quite scarce in meeting this demand. In this paper we will present about these challenges, how they impact the outlook of More Moore technologies and 3D architectures in this interconnect-scarce era.

“Real 3D” integration 3DIC Integration in its true definition [1] has a long history. As early as 1985, Richard P. Feynman expressed this vision [2]: “Another direction of improvement of computing power is to make physical machines three dimensional instead of all on a surface of a chip. That can be done in stages instead of all at once you can have several layers and then add many more layers as time goes on” [2].

This work presents a new methodology to investigate in-situ the impact of vertical stress on the electrical characteristics of semiconductor devices. It is applied for the first time on III-V Heterojunction Bipolar Transistors (HBT). It combines a nanoindenter, which is used to apply controlled vertical forces on the sample surface, with in-situ electrical measurements using micro probes. The HBT devices are shown to be significantly affected by vertical stress: both the current and the capacitance show a reduction with increasing compressive vertical stress. The observations are confirmed by TCAD simulations This method can be employed to extract the sensitivity of advanced devices to vertical (out-of-plane stress) which is a growing concern in packaging and 3D integration.

CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. Increasing resistance of the interconnect and increasing device parasitics limit the gains from any device improvement because of voltage drops. In this paper we will address various mitigation approaches in both technology and design to enable PPA (Performance-Power-Area) scaling for the 5 nm technology node and beyond. Technology solutions include low-k device spacers, wrap-around contact for improved device parasitics and non-Cu based interconnects for improved interconnect resistance. Design solutions focus on improving cell drive by optimally sizing the device and focus on key layout constructs for lowering the impact of parasitics while enabling much more compact standard cells. Finally, we point out challenges of increasing power density by scaling and tightening defectivity control, particularly in 3D integration.

The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

In the version of this Review Article originally published, the labelling of the reflected beam in Fig. 4a was incorrect. This has now been corrected in the Review Article.

The technology and healthcare industries have been deeply intertwined for quite some time. New opportunities, however, are now arising as a result of fast-paced expansion in the areas of the Internet of Things (IoT) and Big Data. In addition, as people across the globe have begun to adopt wearable biosensors, new applications for individualized eHealth and mHealth technologies have emerged. The upsides of these technologies are clear: they are highly available, easily accessible, and simple to personalize; additionally they make it easy for providers to deliver individualized content cost-effectively, at scale. At the same time, a number of hurdles currently stand in the way of truly reliable, adaptive, safe and efficient personal healthcare devices. Major technological milestones will need to be reached in order to address and overcome those hurdles; and that will require closer collaboration between hardware and software developers and medical personnel such as physicians, nurses, and healthcare workers. The purpose of this special issue is to analyze the top concerns in IoT technologies that pertain to smart sensors for health care applications; particularly applications targeted at individualized tele-health interventions with the goal of enabling healthier ways of life. These applications include wearable and body sensors, advanced pervasive healthcare systems, and the Big Data analytics required to inform these devices.

This work investigates, in detail, the electrically gate-all-around (eGAA) Hexagonal NW FET (HexFET) which combines the high current drive of FinFETs with the excellent electrostatic robustness of conventional Gate-All-Around Nanowire (GAA NW) FETs. We evaluate HexFET as a potential successor to FinFET for 5nm node logic and SRAM applications using first principles atomistic-based modeling, calibrated 3D numerical device simulations, and circuit-level benchmarking. From this, we conclude that the eGAA HexFET architecture offers superior performance to both FinFET and GAA NW FET for 5nm node applications.

Internet of Things (IoT) offers a seamless platform to connect people and objects to one another for enriching and making our lives easier. This vision carries us from compute-based centralized schemes to a more distributed environment offering a vast amount of applications such as smart wearables, smart home, smart mobility, and smart cities. In this paper we discuss applicability of IoT in healthcare and medicine by presenting a holistic architecture of IoT eHealth ecosystem. Healthcare is becoming increasingly difficult to manage due to insufficient and less effective healthcare services to meet the increasing demands of rising aging population with chronic diseases. We propose that this requires a transition from the clinic-centric treatment to patient-centric healthcare where each agent such as hospital, patient, and services are seamlessly connected to each other. This patient-centric IoT eHealth ecosystem needs a multi-layer architecture: (1) device, (2) fog computing and (3) cloud to empower handling of complex data in terms of its variety, speed, and latency. This fog-driven IoT architecture is followed by various case examples of services and applications that are implemented on those layers. Those examples range from mobile health, assisted living, e-medicine, implants, early warning systems, to population monitoring in smart cities. We then finally address the challenges of IoT eHealth such as data management, scalability, regulations, interoperability, device–network–human interfaces, security, and privacy.

We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal wraparound contact (CWAC) to reduce contact resistance with minimum parasitic capacitance penalty, metal gate (MG) stressor to improve N-channel mobility, EUV single exposure metal patterning with improved tip-to-tip patterning technique for maximum mask count reduction, and Al metallization to reduce metal & via resistances, however still requiring a validation of the proposed electromigration (EM) risk mitigation. We show that finFET can still be extended to 5nm technology to meet Power-Performance-Area-Cost (PPAC) targets. EGAA NW could enable further 50mV less supply voltage to significantly improve 5nm PPAC scaling.

Rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore’s law on its traditional scaling path.

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.

By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling and provides 34% energy gain from 6T cells. The loss in speed of 15% can be recovered by different front-end solutions. Air gap spacers are the most efficient booster and provide an extra 16% gain in energy. Lateral Nanowires can compete in speed with FinFETs with an extra energy gain of 12% if tight vertical pitch of 10 nm between wires can be achieved.

We propose complete technology-design-system cooptimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.