Effective algorithms have been invented for post-routing redundant via insertion (RVI). However, implementations of these algorithms often ignore some practical issues. In this article, we implement a post-routing RVI algorithm that takes into account interconnect contexts during RVI. Experimental results show that our context-aware RVI on average raises via1 (vias between metal layer 1 and 2) insertion rate from 37.4% to 72.1% and total insertion rate from 72.5% to 85.8%. On average, it increases RVI rate of critical paths by 3.6%. Besides, with redundant pin-area minimization, our approach reduces metal 1 and metal 2 area used for RVI at pins by 3%.

In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. Logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured ASIC design flow using most of the existing tools. VCLBs are employed to construct cell libraries, each consisting of a few tens of cells to several hundred cells. This broad spectrum of VCLB architectures is evaluated in terms of delay, power, and area of designs.

A reticle exposure plan for a multi-project wafer (MPW) defines the sites where reticle images are printed on the wafer. In this paper, we propose an approach to finding a reticle exposure plan that minimizes the wafer fabrication cost rather than the number of wafers. Our approach achieves up to 20% reduction in wafer fabrication cost for low-volume production and 4% reduction for higher volume production when compared to a method that simply minimizes the number of wafers. We also find that printing partial reticle images on wafer edge does not pay off for low-volume production and is marginally better for higher volume production.