In this paper, we present a powerful global router that gets the first place in the ICCAD 2024 CAD Contest Problem D: Chip-Level Global Router, proposed by MediaTek. This challenge requires consideration of several constraints during the global routing stage. Our approach uses an efficient method to determine routing sequences, decompose multi-pin nets, and apply the $A^{*}$ algorithm to route each net, minimizing overflow and computation time. Finally, we present our scores and runtime. The result shows that, on average, our chip-level global router outperforms the other first-place solution by $\mathbf{2 0. 8 6 \%}$, demonstrating its superior efficiency.

We present a novel approach to solving the floorplanning problem by leveraging fine-tuned Large Language Models (LLMs). Inspired by subitizing–the human ability to instantly and accurately count small numbers of items at a glance–we hypothesize that LLMs can similarly address floorplanning challenges swiftly and accurately. We propose an efficient representation of the floorplanning problem and introduce a method for generating high-quality datasets tailored for model fine-tuning. We fine-tune LLMs on datasets with a specified number of modules to test whether LLMs can emulate the human ability to quickly count and arrange items. Our experimental results demonstrate that fine-tuned LLMs, particularly GPT4o-mini, achieve high success and optimal rates while attaining relatively low average dead space. These findings underscore the potential of LLMs as promising solutions for complex optimization tasks in VLSI design.

In this paper we present a 4.5-track standard cell library using ASAP7 PDK extended to support buried-power rails and backside metal wires for power distribution. This work showcases a successful implementation of a 4.5-track cell library by a co-optimization performed at process, cell, and chip levels. Experimental results show that the 4.5-track cell library can improve the ratio of timing performance to area and the ratio of timing performance to power dissipation by 43% and 27% respectively when compared with the results obtained with a six-track cell library.

Functional verification and debugging are critical bottlenecks in modern System-on-Chip (SoC) design, with manual detection of Advanced Peripheral Bus (APB) transaction errors in large Value Change Dump (VCD) files being inefficient and error-prone. Addressing the 2025 ICCAD Contest Problem D, this study proposes an automated error diagnosis framework using a hierarchical Random Forest-based architecture. The multi-stage error diagnosis employs four pre-trained binary classifiers to sequentially detect Out-of-Range Access, Address Corruption, and Data Corruption errors, prioritizing high-certainty address-related faults before tackling complex data errors to enhance efficiency. Experimental results show an overall accuracy of 91.36

As modern System-on-Chip (SoC) designs become increasingly complex, ensuring the reliability of embedded Static Random-Access Memory (SRAM) is a critical challenge, particularly in AI-driven robotics and automation systems. This study proposes an optimized RTL-BIST (Built-In Self-Test) IP Core, developed using High-Level Synthesis (HLS) techniques, to enhance the efficiency and effectiveness of embedded memory testing. The proposed IP core integrates an improved March mSR+ algorithm, significantly increasing fault coverage-particularly for Destructive Read/Write Coupling Faults (CFdrd)-achieving 100 % detection capability. Implemented and validated on an FPGA platform, the RTL-BIST IP core demonstrates superior fault detection and repair mechanisms, while minimizing power consumption and hardware overhead. Experimental results confirm that March mSR+ achieves the highest fault coverage (88.89 %) among tested algorithms, while maintaining the lowest total power dissipation (125.38 mW). These findings validate the proposed IP core as a high-performance, low-power, and scalable solution for embedded memory reliability in advanced semiconductor, AI-powered robotics, and automation applications. By ensuring robust memory testing, this study contributes to the development of highly reliable AI-driven robotic systems, where fault-tolerant embedded memory is essential for real-time decision-making and autonomous operations.

On-grid pin access is necessary for 1-D regular layout design. It is also instrumental to detailed routing efficiency. As semiconductor technology advances, on-grid pin access becomes a distant goal due to increasing discrepancy between contacted polysilicon pitch (CPP) and M1 pitch (M1P). Though the multiple-layout approach to this problem was proposed for some specific case, no investigation into its impact on chip-level routing is found. In this paper, we generalize the multiple-layout approach. We design a 7.5-track standard cell library for the case of the ratio CPP/MIP = 3/2 to study the impact of the multiple-layout approach on chip-level routing. The experiments for this specific case show that the multiple-layout approach can achieve not only on-grid pin accesses but also 46% to 83% fewer DRC violations with 28% to 50% less runtime at the expense of 5% to 13% increase in the longest path delay. If on-grid pin access is a must, the increase in the longest path delay is the price for fulfilling such a requirement.

Pin access has been crucial to detailed routing for obtaining DRC violation-free standard cell designs. In this article we propose exploiting the routing intents of a net to optimize pin access point selection. We also propose a method to enable a commercial router to assess the effectiveness of our approach. Experimental results show that our approach can significantly reduce DRC violations and achieve on average 1.4% similar to 2% smaller wire length at the expense of 0.4% similar to 2% more vias when compared with the results obtained using the access points selected by a commercial router. Our approach also performs much better than a state-of-the-art approach based on dynamic programming.

The work presented in this paper extends ASAP7 PDK to support buried power rail and backside metal technologies. With these two technologies, more resources can be spared not only for routing internal signals of standard cells but also for routing inter-cell signals. Better chip-level routability leads to a higher core utilization and, as a result, a smaller chip area. We use this PDK to design a six-track standard cell library. Our experimental results show that we can on average reduce chip area by 13.1%, worst negative slack by 9.4%, total negative slack by 42%, total wire length by 5.8%, and via count by 19.9%

This paper presents a method to determine which inverted input cells (IICs) should be included into a standard cell library designed with a 7 nm process technology. Standard cells with some inverted inputs not only could reduce the number of cells in a design but also possibly eliminate the area overhead (diffusion breaks) required for isolating the inverters from the standard cells without inverted inputs. Our experimental results show that employing a 7 nm standard cell library with 21 IICs derivedfrom only 8 master cells could save on average 8.4% cells and 2.8% total cell area per circuit without worsening timing performance.

This paper presents a methodology to improve pin accessibility of standard cells under power/ground (P/G) stripes. Two strategies are used. First, hard-to-access cells located under M3 P/G stripes are swapped with easily accessible cells in close proximity. Second, filler cells are added at some places under P/G stripes to push the hard-to-access cells away from P/G stripes. Experimental results show that cell swapping can reduce DRC violations by 86% while still averagely maintaining timing performance. Filler cell insertion can reduce DRC violations by 81% but less effective in maintaining timing performance.

In this paper we present several approaches to improving pin accessibility of standard cells designed with ASAP7 PDK. These approaches are refining pin layout, using double-row height cells, using double-row height cells with must-join pins, inserting dummy polys into hard-to-access cells, and excluding cells with poor pin accessibility from a cell library. We create five 6-track standard cell libraries using these approaches. We also look into pin-access challenges intrinsically tied to a process technology. Experimental results show that inserting dummy polys into hard-to-access cells and refining pin layout are more effective approaches to mitigating pin access problem.

In this article we present three 6-track standard cell libraries based on ASAP7 PDK which is extended to include three technologies, contacts over active gates (COAG), fin depopulation, and a diffusion break taking a space of one contacted poly pitch (CPP). All these three technologies are invented to reduce standard cell area and thus chip area. Experimental results show that fin depopulation solely can achieve 8.3% area saving, COAG brings about another 9.3%, and a diffusion break of 1 CPP adds another 2.5% more. These three technologies all together bring about 20% area saving when compared with that obtained by employing a 7.5-track cell library without excising these three technologies.

It has been known for some time [KIR83, MIT86] that Markov chain techniques can be applied to solving combinatorial optimization problems. Under certain conditions a nonstationary Markov chain of states in the solution space of the combinatorial problem asymptotically converges in probability to a global minimum. A similar set of ideas was introduced earlier in the domain of automata theory for adaptive optimization of the unknown function of parameters. Random search algorithms were interpreted there as stochastic automata and were investigated by means of discrete Markov chains. In this paper we prove the equivalence between some popular randomized algorithms for combinatorial optimization (simulated annealing, SA), certain types of stochastic automata (S-type GH-stochastic automata with variable structure), and non-stationary Markov chains. By using Markov chain techniques, it was demonstrated that many stochastic automata have properties similar to those of simulated annealing and are not inferior to SA in computations. 544Large computational experiments were conducted on a network of Apollo computers.

In this work we first look into the standard cell library enclosed with ASAP7 PDK to uncover the root causes that limit the use of this cell library for research and development. In view of the root causes, we propose a revised technology LEF file for the cell library. Experimental results show that, with the revised technology LEF file, an industrial router can complete place&route of a design up to 180 thousand cells with a core utilization of 90%. We further add 23 frequently used cells into the cell library and reshape pin layout of each cell to increase on-grid pin accessibility. The designs with the improved cell library are more routable and have fewer DRC errors.

In this article we propose a systematic method to study how increasing use of double-row height cells would impact placement and routability of a circuit. To facilitate our study, we handcraft 87 standard cells, each of which has two layouts of the same area, one designed with single-row height and the other designed with double-row height. Experimental results show that the compromise made by placement, later turned into routability degradation, for handling double-row height cells reaches its peak when a circuit has about 30% of the cells being double-row height cells if placement is done with a core utilization of 90%. It is about 40% if a core utilization of 80% is employed.

In this article we present a concept called morphed layouts which are layouts of a standard cell with different footprints on the pins of each layout. We propose two approaches to exploiting morphed layouts for pin length reduction. The first approach is performed after placement but before routing. This approach enables design space exploration to seek best trade-off between total wire length and via count. It can obtain better results than the previous work when dealing with large circuits. The second approach is applied to a routed design, which can always achieve pin length reduction without via count increase. It can on average reduce total pin length by 12.1% and total wire length by 3.4%.

Owing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches for the multilayer obstacle-avoiding rectilinear Steiner tree (ML-OARST) problem are thus nonmaze routing-based approaches for runtime issues, yet they cannot be directly applied to deal with additional constraints such as variant edge weights on a routing layer. In this article, we propose the maze routing-based methodology with bounded exploration and path-assessed retracing to reduce runtime and routing cost for the constrained ML-OARST construction problem. The exploration of maze routing is bounded to reduce the runtime; the costs of connecting pins are computed to select Steiner points in the retracing phase. To further reduce the routing cost, we develop a Steiner point-based ripping-up and rebuilding scheme for altering tree topology. Experimental results on industrial and randomly generated benchmarks demonstrate that the proposed methodology can provide a solution with good quality in terms of routing cost and has a significant speedup compared to traditional maze routing. A commercial tool is also used to show the effectiveness of the proposed methodology.

This paper presents an algorithm for finding array structures in a layout design. The algorithm can find all the regular layout structures from a flattened layout design without knowing its building blocks beforehand. A potential application of this work is to reduce layout DRC and lithography check time. Experimental results show that our algorithm is efficient and robust.

This article presents our experience of designing double-row height standard cell libraries and their use for chip designs. Seven cell libraries are designed based on the 15nm process technology stipulated in FreePDK15. A single-row height of 7.5 M2 tracks is used as a basis for designing double-row height cells. Two minimum-sized transistors, one having two fins and the other having four fins, are employed to design 1X drive-strength cells. Among the seven libraries, two libraries consist of only single-row height cells. The other five libraries each consist of partly single-row height cells and double-row height cells. Our experiments show that a double-row height library can achieve on average -2% to 21% area saving and -23% to 19% smaller power-delay-area product. Our results also show that using a large minimum-sized transistor for designing a double-row height library is not viable if extensive transistor folding is required.

The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition. We hope that the contest evaluation frameworks and benchmarks boost research on these critical problems and help EDA community discover novel, efficient, high-quality solutions to advance the state-of-the-art in EDA.