By combining React ive Ion Etching (RIE), metal evaporat ion technique and polystyrene (PS) nanosphere lithography, we demonst rate fabrication of sub 100 nm 2D st ructures on silicon subst rates. In this work, we concentrated on the self-organizat ion of PS beads (diameters ~ 100 nm) dispersed on silicon subst rate. Afterwards, the effect of dry etching by RIE-O2 on a monolayer and bilayers of PS beads was also studied. Our goal was to decrease the size of the beads from 100 to 40nm and to change it s form from simple to a complex st ructure. In the final step, by using evaporat ion technique we deposited metal on monolayer st ruct ure. After lift -off we obtained a metal film with holes and nanotriangles. Finally, as prepared monolayers of PS beads and pat terned metal film containing holes and nanotriangle were used as etching masks to realize different sub-100 nm silicon st ructures such as nanospheres, nanocones, nanoholes, nanotriangles, nanodot s.

2 cm diameter hydrothermal ZnO crystals were grown and then made into substrates using both mechanical and chemical-mechanical polishing (CMP). CMP polishing showed superior results with an (0002) Ω scan full width half maximum (FWHM) of 67 arcsec and an root mean square (RMS) roughness of 2 Å. In comparison, commercial melt-grown substrates exhibited broader X-ray diffraction (XRD) linewidths with evidence of sub-surface crystal damage due to polishing, including a downward shift of c-lattice parameter. Secondary ion mass spectroscopy revealed strong Li, Fe, Co, Al and Si contamination in the hydrothermal crystals as opposed to the melt-grown substrates, for which glow discharge mass spectroscopy studies had reported high levels of Pb, Fe, Cd and Si. Low temperature photoluminescence (PL) studies indicated that the hydrothermal crystal had high defect and/or impurity concentrations compared with the melt-grown substrate. The dominant bound exciton for the melt-grown substrate was indexed to Al. ZnO films were grown using pulsed laser deposition. The melt-grown substrates gave superior results with XRD (0002) Ω and 2θ/Ω WHM of 124 and 34 arcsec, respectively. Atomic force microscope measurements indicated a low RMS roughness (1.9 nm) as confirmed by fringes in the XRD 2θ/Ω scan. It was suggested that the improvement in XRD response relative to the substrate might be due to “healing” of sub-surface polishing damage due to the elevated Ts used for the growth. Indeed the c-lattice parameter for the homoepitaxial layer on the melt-grown substrate had become that which would be expected for strain-free ZnO. Furthermore, the stability of the PL peak positions relative to bulk ZnO, confirmed that the films appear practically strain free.

The interaction of Co thin films on atomically flat ZnO(000–1) has been investigated by low energy electron diffraction (LEED), scanning tunneling microscopy (STM) and Auger electron spectroscopy (AES). A high density of islands nucleates at the earliest stages of the growth and a subsequent Wolmer–Weber growth of these islands is observed. Upon annealing at 600 °C, an atomically flat surface (Zn,Co)O(000–1) is restored due to the diffusion of the Co into the semiconductor.

The effect of annealing of Co∕ZnO(0001) was studied by scanning tunneling microscopy, low energy electron diffraction, and Auger electron spectroscopy. At room temperature, Co forms islands on ZnO. Annealing up to 940K leads to coalescence of the islands. At 970K, Co diffuses into ZnO where it partially replaces Zn. A model of the Auger intensities, based on exponential attenuation with thickness and including correction for matrix effects, confirms this interpretation and suggests that the fraction of Zn replaced by Co is near 50% or higher.

In this paper, we report new results on polishing and characterization of thick aluminium nitride (AlN) layers grown on 2- and 3-inch electrically conducting 4H-SiC on-axis substrate. As thick as 10-22 mu m AlN layers were deposited on Si-face by stress control hydride vapor phase epitaxy. Rough as-grown layers were polished to provide epi-ready surface for device epitaxy. Surface morphology and surface defects of AlN were studied by atomic force microscopy, optical microscopy and scanning electron microscopy. The root mean square surface roughness was drastically decreased from 470 angstrom for as-grown surface to less than 3 A and the peak to valley value was decreased from 345 nm to less than 3 nm. As-grown and polished epilayer thickness homogeneity, verified by Fourier transform infrared (FTIR) reflectivity, is better than 5%. Structural properties were investigated by X-ray diffraction (XRD). XRD rocking curves were measured in omega-scanning mode for the (00.2) and (10.2) reflections. (c) 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

We established a cleaning procedure to obtain atomically flat $000 \bar {1}$ surfaces from pressurized melt grown ZnO using ex‐situ and in‐situ processing. The ex‐situ chemical cleaning consisted in removing the surface fluid layer and contaminants from the surface. The physical in‐situ procedure used sputtering‐annealing cycles to clean and reconstruct the surface. 3 key parameters were in‐situ investigated: the annealing time, the annealing temperature and the sputtering energy. Investigations were carried out by means of Low Energy Electron Diffraction (LEED), Auger Electron Spectroscopy (AES), X‐ray Photoemission Spectroscopy (XPS), Time of Flight of Secondary Ion Mass Spectrometry (ToF‐SIMS), Atomic Force Microscopy and Spectroscopy (AFM and AFS) and Scanning Tunnelling Microscopy (STM). (© 2006 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

We established a cleaning procedure to obtain atomically flat (000 (1) over bar) surfaces from pressurized melt grown ZnO using ex-situ and in-situ processing. The ex-situ chemical cleaning consisted in removing the surface fluid layer and contaminants from the surface. The physical in-situ procedure used sputtering-annealing cycles to clean and reconstruct the surface. 3 key parameters were in-situ investigated: the annealing time, the annealing temperature and the sputtering energy. Investigations were carried out by means of Low Energy Electron Diffraction (LEED), Auger Electron Spectroscopy (AES), X-ray Photo-emission Spectroscopy (XPS), Time of Flight of Secondary Ion Mass Spectrometry (ToF-SIMS), Atomic Force Microscopy and Spectroscopy (AFM and AFS) and Scanning Tunnelling Microscopy (STM).

In this study, we established a cleaning procedure to obtain atomically flat (000-1) surfaces from pressurized melt grown ZnO. Ex situ chemical cleaning removes fluid layer and trapped contaminants from the surface. This was followed by cycles of sputtering and annealing in ultrahigh vacuum. It is critical that the ion energy be high enough to produce small and highly mobile molecular fragments. On the other hand, annealing must be done at moderate temperatures to avoid segregation of potassium to the surface. Secondly, the interaction of Co thin films on atomically flat ZnO(000-1) has been investigated by low energy electron diffraction, scanning tunneling microscopy, and Auger electron spectroscopy. A high density of islands nucleates at the earliest stages of the growth and a subsequent Volmer-Weber growth of these islands is observed. Upon annealing at 550°C, an atomically flat surface (Zn,Co)O(000-1) is restored due to the diffusion of the Co into the semiconductor.

In this work, we have investigated the 3C-SiC re-growth on planarized 3C-SiC epitaxial layers, grown on (001)Si, after the application of a chemical mechanical polishing (CMP) process. A specific polishing process was developed for 3C-SiC to achieve a flat, high-quality surface. The interface between the deposited 3C-SiC and the polished 3C-SiC on Si film was studied by TEM characterization to determine if defects appear at this interface. It was observed that no additional defects were nucleated at the interface. The resulting re-grown film roughness, as a function of film thickness, was studied and is reported along with recommendations for future work.

Unlike other techniques for surface cleaning/etching such as dry etching (RIE, ICP), the new polishing process does not degrade Schottky diode forward characteristics. Thus, apart from the promising improvement of starting material quality, fine surface polishing seems to offer significant advantages in terms of increasing manufacturing yield.

The use of flash lamp annealing for processing semiconductor materials is outlined. Specific applications include ultra-shallow junction formation and heteroepitaxial growth of improved quality thin films of cubic silicon carbide. It is demonstrated that flash lamp annealing holds great promise as a technique for fabricating novel devices.

Surface treatment is a key technological parameter in the microelectronics technology and especially for SiC devices since high temperatures must be used for implanted impurities annealing and crystal damage recovery. In this work we take profit of a novel fine polishing process developed by NOVASIC to improve the electrical characteristics of Boron and Aluminium implanted Schottky diodes, which are surface quality highly sensitive devices. The mentioned fine polishing process allows to remove a layer thickness of 100nm to 3000nm on the surface of a processed SiC wafer, reducing the surface roughness to RMS of 1Å. The impact of this process on the electrical properties of the samples shows a general improvement of characteristics reproducibility, reduction of leakage current and improvement of breakdown of Boron implanted diodes.

The excellent chemical and mechanical properties of SiC make, paradoxically, damage free surface preparation a real challenge. The preparation of SiC wafers can be described in four successive stages corresponding to different objectives:

This paper summarises latest advancements regarding FLASiC (Flash lamp supported deposition of 3C-SiC) as a new approach to produce high quality SiC-Si heteroepitaxial material. This concerns description of the process and equipment, microstructural results and modelling aspects. In this manner a new era of nanoscale liquid phase epitaxy could be born.