The dependability assessment of critical systems must consider the emulation of transient faults, as they pose an important dependability threat for modern VLSI designs. FPGA-based systems are dominated by bit-flips in configuration memory (CM), which are relatively easy to emulate using partial runtime reconfiguration (RTR) FPGA fault injection (FFI) approaches. However, when FPGA is used as an ASIC prototyping platform, transient fault models representative of ASIC designs must be considered, such as bit-flips in sequential logic cells (Flip-Flops and on-chip RAM blocks). Existing RTR-FFI approaches do not adequately cover these faults, as they require the orchestrated manipulation of multiple CM bits for each target logic cell, and the location of these CM bits is unknown (not documented) for modern FPGA generations. This work experimentally formalises the mapping of the necessary CM bits, proposes an enhanced RTR-FFI methodology to emulate bit-flips in registers and on-chip RAMs of current-generation AMD Ultrascale+ FPGAs, and provides an upgraded publicly available open source FFI tool (BAFFI, https://gitlab.com/selene-riscv-platform/DAVOS ) supporting the proposed methodology. The validity of the proposed FFI approach is demonstrated by comparison with gate-level simulation-based fault injection in a case study of two soft-core processors (MC8051 and NOEL-V).

Convolutional Neural Networks (CNNs) are increasingly deployed in safety-critical systems with stringent dependability requirements. While early design exploration relies on high-level Python models, incorporating dependability mechanisms into them is typically a manual, intrusive process that intertwines functional and non-functional concerns. This paper proposes an automated framework grounded in the separation of concerns (SoC) principle to support dependable CNN engineering. By leveraging Python-native metaprogramming capabilities, such as decorators, wrappers, runtime hooks, and Abstract Syntax Tree transformations, dependability functionalities can be transparently woven into original PyTorch models. The proposed approach enables systematic early-stage dependability assessment and automated protection deployment without manually tampering with the core functional code.

Spiking Convolutional Neural Networks (S-CNNs) are a promising neuromorphic AI approach that combine the spatial feature extraction capabilities of convolutional neural networks with the low-latency and energy-efficient event-driven processing of Spiking Neural Networks (SNNs). While S-CNNs are increasingly considered for embedded and edge applications, their deployment in safety- or mission-critical domains requires a deeper understanding of their resilience to hardware faults. In particular, memory faults may significantly affect the temporal dynamics and inference behavior of these architectures, leading to silent accuracy degradation or unpredictable outputs. This paper analyses the impact of memory faults through an extensive fault injection campaign in an S-CNN developed by our research group. The findings of this work provide valuable insights into the reliability of Spiking Neural Networks and contribute to the design of more robust AI accelerators and embedded intelligent systems. This work represents a step toward dependable neuromorphic computing platforms suitable for critical applications where correctness, predictability, and efficiency are essential.

In the spatial sector, there is a strong demand for the incorporation of Artificial Intelligence (AI) capabilities into artificial satellites to improve their reliability, reduce costs, and increase their autonomy. Specially in the New Space sector, it is very important to have onboard systems with AI capabilities with a very low SWaP (Size, Weight, and Power) metric with prices much lower than the solutions used in traditional space systems. We introduce here the work of our research group within the NeuroAI4Space project. The final objective is to develop a scalable radiation-hardening methodology for deploying a neuromorphic IP core on commercial FPGAs and non-rad-hard ASICs in LEO missions. The approach applies selective hardware fault-tolerance techniques, based on mission requirements, combining redundancy, vulnerability analysis, and FPGA-based fault injection to balance reliability, performance, and cost. The outcome will be a validated framework that ensures reliable, lowcost, and energy-efficient onboard neuromorphic computing for Earth observation applications.

Error Correction Codes (ECCs) are increasingly used in safety-critical systems, such as hardware accelerators for cryptographic computations and neural network inference. These systems require high reliability, making ECCs essential for mitigating soft errors and improving fault tolerance. Thus, the demand for efficient ECC implementations is rising, necessitating faster design and deployment processes. Traditional hardware design approaches, such as Register-Transfer Level (RTL) development, can be time-consuming and very complex. High-Level Synthesis (HLS) enables the automatic transformation of C-based ECC models into hardware descriptions, reducing development effort while allowing design-space exploration. This methodology facilitates rapid prototyping and optimization, enabling the evaluation of different architectural choices without manually modifying the RTL code. However, coding styles, algorithmic transformations, and optimization strategies in C-based can directly affect the synthesized hardware's performance metrics, including area utilization, power consumption, and latency. This work provides initial insights into how different C-based ECC design choices influence the final hardware implementation. To do this, we have analyzed synthesis results under various ECC configurations.

Convolutional Neural Networks (CNNs) are widely adopted in Artificial Intelligence applications, particularly in computer vision and other deep learning tasks. Their performance relies on millions of parameters, including weights and biases, which are optimized during training, stored, and utilized during inference. Traditionally, these parameters are represented using the 32-bit IEEE-754 single-precision floating-point format. However, research has shown that excess precision in this format is not always required to maintain accuracy, motivating the adoption of reduced-precision 16-bit formats. A natural progression of this trend is representing real numbers using 8-bit formats. However, existing proposals often suffer from precision loss, negatively impacting CNN accuracy. In this extended abstract, we propose a novel 8-bit floating-point format designed to enhance reliability in CNNs, due to its reduced memory footprint, enough precision, and well-fitted range. We evaluate its advantages and limitations through comparative analysis. Initial findings suggest that our format improves computational efficiency while preserving accuracy comparable to 32-bit networks, increasing reliability. However, further experimental validation is necessary.

Error-Correcting Codes (ECCs) are essential for achieving fault tolerance in hardware accelerators deployed in safety-critical applications, such as those used to accelerate neural network inference and cryptographic processing. High-Level Synthesis (HLS) enables the automatic translation of ECC models described in C/C++ into synthesisable hardware, but the structure and style of such descriptions significantly affect circuit-level efficiency. This work investigates five ECC coding strategies, each representing a distinct combination of syndrome computation and correction mechanisms. These strategies are implemented using C++ integers or using arbitrary precision integers provided by the HLS AP_INT library. Considered ECC protection levels are Single, Double, and Triple-Adjacent Error Correction for dataword lengths of 8, 16, and 32 bits. This results in a total of 90 ECC configurations synthesised for both ASIC and FPGA targets, yielding 180 hardware implementations in total. Hardware metrics, including area, power consumption, latency, and resource usage, are evaluated and analysed using analysis of variance (ANOVA) to determine the influence of each design factor. Results indicate that logic-oriented descriptions generally yield more efficient circuits for ASICs, whereas memory-centric implementations perform better on FPGAs equipped with dedicated BRAM. The AP_INT library has minimal statistical impact but provides finer control over bit-widths. Based on these findings, a set of high-level modelling guidelines is proposed to guide the efficient high-level implementation of ECCs via HLS.

Quantized Convolutional Neural Networks (QCNNs) are widely adopted in resource-limited environments due to their reduced memory footprint, lower power consumption, and faster execution. Hardware (HW) accelerators further enhance these benefits by optimizing QCNN execution for available resources, a crucial aspect in embedded systems. Typically, the development of neural networks begins with a software (SW) model, later refined and implemented in HW. Leveraging this initial SW model for early robustness assessments is an attractive approach, as it allows fault tolerance evaluation before committing to HW implementation. However, for such assessments to be meaningful, they must accurately reflect the fault behavior in HW. This paper examines the limitations of naive fault injection in SW-based QCNN models and demonstrates how they can lead to misleading conclusions about HW robustness. The key issue arises from the internal multi-component representation of quantized parameters, which differs from direct floating-point storage. Our analysis highlights that simplistic bit-flip injections in SW do not necessarily translate to equivalent faults in HW, leading to inaccuracies in robustness evaluation. While we do not propose a specific fault injection methodology, we identify critical challenges that must be addressed to ensure that early-stage SW evaluations provide valid, cost-effective insights into QCNN resilience in HW.

Convolutional Neural Networks (CNNs) have accomplished significant success in various domains, including transportation, health care and banking. Millions of weights, loaded from main memory into the internal buffers of CNN accelerators, are repeatedly used in the inference process. Accidental and malicious bit-flips targeting these buffers may negatively impact the CNN's accuracy. This paper proposes a methodology to tolerate the effect of (multiple) bit-flips on floating-point-based CNNs using the non-significant and the invariant bits of CNN parameters. The former, determined after fault injection, do not significantly affect the accuracy of the inference process regardless of their value. The latter, determined after analyzing the network parameters, have the same value for all of them. Slight modifications can be applied to carefully selected parameters to increase the number of invariant bits. Since nonsignificant and invariant bits do not require protection against faults, they are employed to store the parity bits of error control codes. The methodology preserves the CNN accuracy, keeps its memory footprint, and does not require any retraining. Its usefulness is exemplified through the FP32 and BFloat16 versions of the LeNet-5 and GoogleNet CNNs.

Deploying convolutional neural networks (CNNs) in image classification systems requires balancing conflicting goals, like throughput, power consumption, and silicon area. In safety-critical environments, ensuring acceptable levels of robustness against faults is also of utmost importance. The robustness gains promoted by quantised CNNs entail a loss of accuracy that may be problematic for some applications. Traditional redundancy-based solutions provide high error coverage at the cost of high, and sometimes unaffordable, overheads, especially for resource-constrained solutions. This paper proposes using error correction codes (ECC) to protect the tensors of CNNs from potential inadvertent corruption. Fault injection is used to locate all bits in tensors that, even if corrupted, do not affect the network inference process. These bits are then replaced by computed parity bits. By exploiting the intrinsic robustness of CNNs, no additional memory bits are required to store the parity bits while preserving both the ECC protection guarantees and the CNN inference accuracy. The proposal applies conventional, conservative, and aggressive policies depending on the required degree of protection and the overhead the system can afford. The usefulness of these alternatives is exemplified through a floating-point-based CNN that is prototyped on a programmable logic device. Unlike existing solutions, the approach can be deployed without retraining, using well-known and proven ECCs and at an in-memory zero-space cost.

Using low-precision data types, like the Brain Floating Point 16 (BF16) format, can reduce Convolutional Neural Networks (CNNs) memory usage in edge devices without significantly affecting their accuracy. Adding in-parameter zero-space Error Correction Codes (ECCs) can enhance the robustness of BF16-based CNNs. However, implementing this technique raises practical questions. For instance, when the available invariant1 and non-significant2 bits in parameters for error correction are sufficient for the required protection level, the proper selection and combination of these bits become crucial. On the other hand, if the set of available bits is inadequate, converting nearly invariant bits to invariants might be considered. These decisions impact ECC decoder complexity and may affect the overall CNN performance. This report examines such implications using Lenet-5 and GoogLenet as case studies.

FPGA-based fault injection (FFI) is an indispensable technique for verification and dependability assessment of FPGA designs and prototypes. Existing FFI tools make use of Xilinx essential bits technology to locate the relevant fault targets in FPGA configuration memory (CM). Most FFI tools treat essential bits as black-box, while few of them are able to filter essential bits on the area basis in order to selectively target design components contained within the predefined Pblocks. This approach, however, remains insufficiently precise since the granularity of Pblocks in practice does not reach the smallest design components. This paper proposes an open-source FFI tool that enables much more fine-grained FFI experiments for Xilinx 7-series and Ultrascale+ FPGAs. By mapping the essential bits with the hierarchical netlist, it allows to precisely target any component in the design tree, up to an individual LUT or register, without the need for defining Pblocks (floorplanning). With minimal experimental effort it estimates the contribution of each DUT component into the resulting dependability features, and discovers weak points of the DUT. Through case studies we show how the proposed tool can be applied to different kinds of DUTs: from small-footprint microcontrollers, up to multicore RISC-V SoC. The correctness of FFI results is validated by means of RT-level and gate-level simulation-based fault injection.

The architecture of the LeNet-5 convolutional neural network (CNN) was defined by LeCun in its paper "Gradient-based learning applied to document recognition" (https://ieeexplore.ieee.org/document/726791) to classify images of hand written digits (MNIST dataset). This architecture has been customized to use Rectified Linear Unit (ReLU) as activation functions instead of Sigmoid. It consists of the following layers: conv1: Convolution 2D, 1 input channel (28x28), 3 output channels (28x28), kernel size 5, stride 1, padding 2. relu1: Rectified Linear Unit (3@28x28). max1: Subsampling buy max pooling (3@14x14). conv2: Convolution 2D, 3 input channels (14x14), 6 output channels (14x14), kernel size 5, stride 1, padding 2. relu2: Rectified Linear Unit (6@14x14). max2: Subsampling buy max pooling (6@7x7). fc1: Fully connected (294, 147) fc2: Fully connected (147, 10) The fault hypotheses for this work include the occurrence of: BF: single bit-flip faults S0: single, double-adjacent and triple-adjacent stuck-at-0 faults S1: single, double-adjacent and triple-adjacent stuck-at-1 faults In the memory cells containing all the parameters of the CNN: w: weights (float32) b: biases (float32) Images 200 to 249 from the MNIST dataset have been used as workload. This dataset contains the raw data obtained from running exhaustive fault injection campaigns for all considered fault models, targeting all considered locations and for all the images in the workload. Files information golden_run.csv: Prediction obtained for all the images considered in the workload in the absence of faults (Golden Run). This is intended to act as oracle to determine the impact of injected faults. single_faults/bit_flip folder: Prediction obtained for all the images considered in the workload in presence of single bit-flip faults. There is one file for each parameter of each layer. single_faults/stuck_at_0 folder: Prediction obtained for all the images considered in the workload in presence of single stuck-at-0 faults. There is one file for each parameter of each layer. single_faults/stuck_at_1 folder: Prediction obtained for all the images considered in the workload in presence of single stuck-at-1 faults. There is one file for each parameter of each layer. double_adjacent_faults/stuck_at_0 folder: Prediction obtained for all the images considered in the workload in presence of double adjacent stuck-at-0 faults. There is one file for each parameter of each layer. double_adjacent_faults/stuck_at_1 folder: Prediction obtained for all the images considered in the workload in presence of double adjacent stuck-at-1 faults. There is one file for each parameter of each layer. triple_adjacent_faults/stuck_at_0 folder: Prediction obtained for all the images considered in the workload in presence of triple adjacent stuck-at-0 faults. There is one file for each parameter of each layer. triple_adjacent_faults/stuck_at_1 folder: Prediction obtained for all the images considered in the workload in presence of triple adjacent stuck-at-1 faults. There is one file for each parameter of each layer. Methodology information First, the CNN was used to classify all the images of the workload in the absence of faults to get a reference to determine the impact of faults. This is golden_run.csv file. After that, one fault injection experiment was executed for each of the 16 most significant bits bit of each element of each parameter of the CNN, as previous fault injection experiments showed that the occurrence of the considered faults in the 16 least significant bits does not impact the behaviour of the network. Each experiment consisted in: Affecting the bits (inverting it in case of bit-flip faults, setting it to 0 or 1 in case of stuck-at-0 or atuck-at-1 faults) identified by the mask. Classifying all the images of the workload in the presence of this fault. The obtained output was stored in a given .csv file. Removing the fault from the CNN by restoring the affected bits to its previous value. List of variables (Name : Description (Possible values)) IMGID: Integer number identifying the considered image (200-249). TENSORID: Integer number identiying the parameter affected by the fault (0 - No fault, 1 - conv1.w, 2 - conv1.b, 3 - conv2.w, 4 - conv2.b, 5 - fc1.w, 6 - fc1.b, 7 - fc2.w, 8 - fc2.b). ELEMID: Integer number identiying the element of the parameter affected by the fault (-1 - No fault, [0-2] - conv1.b, [0-74] - conv1.w, [0-5] - conv2.b, [0-149] - conv2.w, [0-146] - fc1.b, [0-43217] - fc1.w, [0-9] - fc2.b, [0-1469] - fc2.w). MASK: 8-digit hexadecimal number identifying those bits affected by the fault ([00000000 - No fault, FFFFFFFF - all 32 bits faulty]). FAULT: String identiying the type of fault (NF - No fault, BF - bit-flip, S0 - Stuck-at-0, S1 - Stuck-at-1). SOFTMAX: 10 decimal numbers obtained after applying the softmax function to the provided output. They represent the probability of the image of belonging to the corresponding category for classification. PRED: Integer number representing the category predicted for the processed image. LABEL: integer number representing the actual category for the processed image.

Although initially considered for fast system prototyping, Field Programmable Gate Arrays (FPGAs) are gaining interest for implementing final products thanks to their inherent reconfiguration capabilities. As they are susceptible to soft errors in their configuration memory, the dependability of FPGA-based designs must be accurately evaluated to be used in critical systems. In recent years, research has focused on speeding up fault injection in FPGA-based systems by parallelising experimentation, reducing the injection time, and decreasing the number of experiments. Going a step further requires delving into the FPGA architecture, i.e. precisely determining which components are implementing the considered design (mapping) and which are exercised by the considered workload (profiling). After that, fault injection campaigns can focus on those components actually used to identify critical ones, i.e. those leading the target system to fail. Some manufacturers, like Xilinx, identify those bits in the FPGA configuration memory that may change the implemented design when affected by a soft error. However, their correspondence to particular components of the FPGA fabric and their relationship with the implementation-level model are yet unknown. This paper addresses whether the effort of reversing an FPGA architecture to filter out redundant and unused essential bits pays in terms of experimental time. Since the work of reversing the complete architecture of an FPGA is titanic, as the first step towards this ambitious goal, this paper focuses on those elements in charge of implementing the combinational logic of the design (Look-Up Tables). The experimental results that support this study derive from implementing three soft-core processors on a Zynq SoC FPGA and show the interest of the proposal.

The benchmarking of security tools is endeavored to determine which tools are more suitable to detect system vulnerabilities or intrusions. The analysis process is usually oversimplified by employing just a single metric out of the large set of those available. Accordingly, the decision may be biased by not considering relevant information provided by neglected metrics. This article proposes a novel approach to take into account several metrics, different scenarios, and the advice of multiple experts. The proposal relies on experts quantifying the relative importance of each pair of metrics towards the requirements of a given scenario. Their judgments are aggregated using group decision making techniques, and pondered according to the familiarity of experts with the metrics and scenario, to compute a set of weights accounting for the relative importance of each metric. Then, weight-based multi-criteria-decision-making techniques can be used to rank the benchmarked tools. The usefulness of this approach is showed by analyzing two different sets of vulnerability and intrusion detection tools from the perspective of multiple/single metrics and different scenarios.

Thanks to their dynamic reconfiguration capabilities, FPGAs are used in application domains ranging from embedded systems to high performance computing. Nevertheless, as FPGAs usually rely on SRAM memories to keep their current configuration, they are highly sensitive to radiation. The robustness of FPGA-based implementations can be improved by tuning the configuration parameters of selected IP cores or EDA tools. As many different parameters can usually be set at several configuration levels, this constitutes a huge design space to be explored. Accordingly, not only suitable techniques are required to sample as many different configurations as possible, but also novel fault injection approaches are necessary to reduce the number of faults to be injected and speed up as much as possible the experimentation as a whole. To accomplish this goal, this paper integrates state of the art FPGA-based approaches to speed up the execution of individual fault injection experiments with a novel proposal that minimises the number of fault injection experiments required to successfully explore the design space with robustness in mind and following a genetic algorithm. This approach is exemplified by tuning the Vivado Design Suite to optimize the robustness and clock frequency of MC8051, AVR, and Microblaze soft-core processors.

The dataset contains the results of fault injection experiments carried out for dependability benchmarking of three soft-core processors (MC8051, AVR, Microblaze) at three design representation levels: Register-transfer level (RTL) HDL model; Implementation-level HDL model (defined in the basis of Xilinx simprim library); Level of FPGA prototype (Xilinx Zynq XC7Z020); Fault injection experiments have been carried out by means of DAVOS toolkit (https://github.com/IlyaTuzov/DAVOS). Installation guide is attached (readme.pdf in the package root directory).

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

The high complexity of new designs and time-to-market pressure have caused design reuse to be at the heart of the common semi-custom hardware design flow. Accordingly, current Electronic Design Automation (EDA) toolchains are developed to support a wide range of hardware description languages, third-party EDA tools, intellectual property cores, and implementation technologies and goals. However, the seamless integration of dependability requirements into such toolchains remains today an open challenge. This paper presents DAVOS, an EDA toolkit supporting assessment, verification, optimisation (design space exploration), and selection (benchmarking) processes for dependability-aware hardware implementations. This toolkit fully automates these processes with efficiency and flexibility in mind, so underlying implementation and analysis phases can be customized to consider alternative off-the-self languages, tools, components and technologies from a dependability perspective. Three different embedded processor models exemplify the design scenarios supported by DAVOS.

Dataset exemplifies an approach of iterative statistical fault injection to assess the robustness of HDL models. Contents: 1. Results of exhaustive fault injection experiments (bit-flip faults) into LEON3 processor model; 2. Interactive querying interface, allowing to obtain custom samples from exhaustive results, and visualize them; 3. Python scripts simulating 3 approaches to statistical fault injection: conservative, error-driven, time-driven. Installation guide: 1. Ensure to have python ver. 2.x installed. Type in terminal (cmd console in Windows): “python --version” – if the output looks like > Python 2.x.x – python is installed. Otherwise download and install 2.x.x distribution: https://www.python.org/ Add python installation path to environment path variable. 2. Ensure to have Web-Server installed (Apache preferable). For instance, XAMPP: https://www.apachefriends.org/index.html 3. Ensure that Web-server is configured to execute CGI scripts, particularly python-scripts: In the 'httpd.conf' file (XAMMP control panel – button config in front of apache module): – search for line Options Indexes FollowSymLinks and add ExecCGI, so the resulting line looks like this: Options Indexes FollowSymLinks ExecCGI – search for #AddHandler cgi-script .cgi, uncomment (remove #), and append “.py” to this line, so the results looks like: AddHandler cgi-script .cgi .pl .asp .py 4. Unpack the contents of *.zip package into the folder on the Web Server. For instance into 'Web-server root folder'/Dataset. The Web-Server root can be configured in the ‘httpd.conf’ file in the DocumentRoot section, for instance: DocumentRoot "F:/HTWEB" ... 5. In the web-browser navigate to the root directory of extracted package: http://localhost/Dataset/index.html