Binary Neural Networks (BNNs) have obtained a strong foothold in the field of machine learning at the edge due to their minimal hardware requirements. However, their energy and performance efficiency remain hindered by frequent data transfer between memory and processors. Computation-in-memory (CIM) architectures address this problem by embedding processing units within the memory. Unfortunately, current implementations of CIM are susceptible to IP piracy attacks through side channels. This paper presents a novel secure periphery scheme for NN accelerators with sequential accumulation that conceals IP information by obscuring the power consumption of the counter responsible for the leakage. This is achieved by combining two innovative techniques: operand schedule randomization and an always-count Gray code counter. The results demonstrate that the proposed design effectively resists power side channel attacks (SCAs). Moreover, Signal-to-Noise Ratio (SNR) and Test Vector Leakage Assessment (TVLA) show safe leakage levels. Compared to the state-of-the-art, our countermeasure reduces area and power overheads by up to 12.7× and 13.3×, achieving only 37% area and 51.2% power overhead with the added protection logic. Notably, this enhanced security comes with zero latency overhead, maintaining the performance of the baseline design.
Due to ambient energy’s inherent instability, intermittent computing is essential for task completion. This work comprehensively explores the spintronic flip-flop implementation in the open-source RISC-V platform. Magnetic tunnel junction (MTJ) has great potential for non-volatile flip-flop (NV-FF) implementation because of its high density, low read and write energy consumption, and compatibility with CMOS process. To the best of the authors’ knowledge, the checkpoint preservation is firstly supported in this work. The proposed non-volatile differential sampling latch (NV-DSL) achieves 7.39 fJ/bit data transfer energy consumption. The phased write strategy reduces write energy by 24.3%. A generalized NV-FF design methodology is further established, achieving a 68.88% area reduction. The power consumption of proposed non-volatile RISC-V processor is reduced by nearly 75%. When performing atomic tasks, the energy consumption and latency are reduced by 61.4% and 43.87%, respectively, compared with the cache scheme.
Majority-Inverter Graph (MIG) emerges as a promising data structure for logic optimization and synthesis, offering a more compact representation for logic functions compared to traditional AND/OR-Inverter graphs. Consequently, the MIG finds widespread application in digital circuit design, particularly in quantum circuits and superconducting adiabatic quantum-flux-parametron logic circuits. Currently, logic optimization techniques for MIG mainly fall into two categories: (i) logic rewriting with predefined more compact sub-structures and (ii) logic resubstitution with already existing logic in the Boolean network. However, the inherent complexity of MIG logic and the limitation imposed by the input scale of sub-structures significantly impact the performance of these methods. To address these challenges, this paper proposes eLogic, a novel depth-oriented MIG logic rewriting framework using e-graphs, to minimize the depth and size of MIG. The eLogic utilizes the e-graphs, a data structure for efficient computation with equalities between terms, to minimize the depth and size of the cone delimited by the cut. The experimental results on the EPFL benchmark demonstrate the effectiveness of eLogic. It is noteworthy that eLogic is open-sourced on https://github.com/Flians/eLogic.
Approximate computing is an emerging design paradigm for error-tolerant applications, such as multimedia processing and neural network acceleration, which enables significant reductions in circuit area, delay, or power consumption through controlled accuracy trade-offs. This paper presents a novel deep reinforcement learning (DRL)-based framework for approximate logic synthesis (ALS) augmented with a backtracking mechanism, aimed at minimizing the area–delay product (ADP) while satisfying error rate constraints. The experimental results demonstrate that our approach can reduce the ADP by up to 92.83%, and 56.79% on average under a 5% error rate constraint.
Computing-in-Memory (CIM) demonstrates exceptional performance on edge AI applications, owing to its in-situ computation capability with minimal data transfer consumption. However, volatile CIMs suffer from inevitable data retention power overhead, while non-volatile MRAM-CIMs still necessitate periodic weight updates constrained by limited memory space, diminishing the intrinsic advantage of CIMs. In this work, we propose a digital SOT-MRAM CIM accelerator with circuit-architecture-operator cross-layer design, achieving double bit density and full utilization of both data transmission bandwidth and computing throughput, thereby satisfying the stringent hardware demands for edge AI applications. Firstly, we propose a refined 2T-1MTJ non-complementary memory cell with an XOR-integrated pre-charged sense amplifier (X-SA), which significantly promotes the storage density and consumes only 6.284 fJ per read-based XOR operation. Then, we devise a channel-flatten data mapping (CFDM) scheme and an operator-aware residual fusion (OARF) structure to full utilize the storage and computing resources. Furthermore, an operator fusion method towards non-linear layers is proposed, achieving an 89.84% size reduction in non-binary parameters. System-level simulations at 40nm demonstrate that our work achieves 284.25 TOPS/W energy efficiency and 5.41 TOPS/mm2 area efficiency with an accuracy of 98.72% (87.78%) on MNIST (CIFAR-10) dataset.
Electromigration (EM) has emerged as a critical reliability concern in advanced technology nodes. Yet the industry-standard Black’s equation lacks generality because its fitted parameters depend strongly on interconnect geometry and can only applied for single segment. In addition, conventional post-layout "analyze-then-fix" verification is reactive and ill-suited to varying mission profiles with stringent EM targets. In this work, we propose EMaper, a cross-level EM-aware optimization framework that couples physics-grounded modeling with early placement and routing. EMaper introduces: (1) a physics-informed EM compact model and thermal simulator, enabling accurate EM estimation across varying geometries and conditions and full-chip thermal analysis; (2) a physically predictive placement and routing framework integrated with physical models. (3) A cross-level framework— spanning from the atomic scale to the physical model to EDA flow—enabling in-design violation prediction and mitigation across varying application scenarios. Experimental results on the ISPD2018 benchmarks demonstrate that EMaper eliminates 92.1% to 100% of EM violations across a variety of operating conditions, with only 4.49% to 16.3% overhead in wirelength and via count. Furthermore, in thermally benign scenarios (e.g., 300 K), EMaper naturally incurs zero overhead, reflecting its self-adaptive optimization capability. These results highlight EMaper’s potential as a practical and scalable solution for EM-aware physical design in modern VLSI flows.
Spatial accelerators are widely deployed for deep neural networks, but their architectural diversity—from hierarchical to dataflow designs—makes accurate architecture–operator modeling difficult, limiting operator optimization and hardware utilization. Existing models abstract hardware as hierarchical chains and operators as loop trees, which cannot capture essential features of modern dataflow accelerators, including heterogeneous processing elements (PEs), uni-directional interconnects, and cross-PE memory hierarchies, leading to inaccurate latency prediction. We propose LATIAS, a unified framework that introduces (1) an architecture graph with uni-directional edges to represent arbitrary topologies, and (2) a dataflow-aware tile-centric notation that augments loop trees with transfer nodes to model diverse dataflows. Building on these, LATIAS further provides a graph-guided tree analysis that accurately resolves tensor residency and latency under hardware constraints. Experiments on representative operators (GEMM, vector, fused vector) and operator shapes extracted from DNNs (BERT, ViT, T5) on Huawei Ascend 910B3 show that LATIAS achieves over 0.99 correlation with runtime measurements—substantially outperforming prior models—and provides actionable insights for architectural design.
Pre-RTL ISA-agnostic simulators have been established for designing heterogeneous systems, but few of them are suitable for evaluating a general-purpose processor (GPP) with custom instructions (CIs). MosaicSim [1], a state-of-the-art ISA-agnostic simulator, still has several limitations for CI design and simulation. First, it shows inaccuracy in simulating GPPs due to an oversimplified performance model. Second, as designed for kernel simulation, it lacks support for running complex real-world benchmarks. Third, it cannot evaluate fine-grained irregular CIs due to the lack of the ability to represent or define them in benchmarks. To this end, we propose CISim, a new ISA-agnostic simulation framework containing an offloader that generates and integrates CIs into benchmarks, along with a simulator capable of executing benchmarks with CIs. Evaluations show that CISim is accurate by validating against Gem5 [2] and achieves higher accuracy than MosaicSim. A case study evaluating CI exploration methods highlights the strength and flexibility of CISim.
Nowadays, warpage effect is becoming one of the main concerns in the manufacture of 2.5-D/3-D IC packages. Numerical simulation of warpage in the design stage by the finite element method (FEM) is required for manufacturability and reliability optimization. 2.5-D/3-D IC packages are generally composed of laminated thin plates with high aspect ratios and complex in-plane material boundaries, leading to intrinsic difficulties in obtaining high-quality hexahedral meshes essential for fast convergence and high-quality results. In this paper, we propose a novel meshing algorithm for efficient generation of sweep hexahedral meshes towards complex 2.5-D/3-D structures. On the basis of the sweep mesh, we utilize a modified 2-D layerwise plate theory to further improve the convergence of the solver. Compared with Ansys Workbench, our meshing algorithm can either reduce the meshing time (74.7× to 221×) and the number of mesh nodes (5.26× to 18.4×), or improve the mesh quality (3.45× to 9.75×) and reduce convergence time of the solver (1.48× to 4.50×), with < 0.5% errors. A 3.75× to 12.6× reduction in convergence time is further achieved with the proposed 2-D layerwise plate theory compared to the 3-D formulation, while maintaining the errors within 3%.
Power side-channel attacks are among the most effective physical attacks, threatening the security of circuits such as cryptographic circuits by exploiting information leakage from their physical implementation. Among various masking and hiding countermeasures that have been proposed, Ring Oscillator (RO)-based solutions are considered low-overhead circuitry addons that can be integrated into different circuits to hide the data dependency of power consumption by adding noise to their power signatures. The Three-Independent-Gate Reconfigurable Field-Effect Transistor (TIG-RFET) is an emerging technology that offers runtime reconfigurability between N-type and P-type operation, supports both low-VT and high-VT modes, and provides an internal wired-AND function, making it a strong candidate for efficient implementation of various hardware security methods. In this paper, we propose a novel reconfigurable RFET-based RO that provides controllable frequency through RFET-based inverters with reconfigurable delay. Using these ROs, we introduce a countermeasure called RETRO, which can generate noise by varying both the amplitude and frequency of power consumption. To evaluate the efficacy of RETRO, we applied it to the Piccolo S-box, a lightweight cryptographic circuit, and simulation results demonstrate that it effectively enhances resilience against Correlation Power Analysis (CPA). Furthermore, we show that reconfigurable frequency broadens the noise spectrum, making filtering considerably more difficult.
Lithography simulation is a critical technology in modern semiconductor manufacturing, yet existing deep learning models often fail to accurately model the complex, long-range optical physics due to the inherent locality of convolution. This limitation results in insufficient simulation fidelity and poses significant challenges for optimization tasks. To overcome this challenge, we introduce LithoMamba, the first generative framework to leverage Mamba for high-fidelity lithography simulation. Our architecture uses a Mamba Generator to model global and long-range optical interactions, while a local, MLP-free Discriminator provides precise, spatial feedback to ensure fine-grained pattern fidelity. This global-local design enables our model to achieve both physical realism and exceptional detail. Our experiments show that LithoMamba outperforms existing methods, both in quantitative and qualitative results. These findings demonstrate the promise of State Space Models for improving lithography simulation and suggest new possibilities for combining physics with generative AI in chip manufacturing.
2.5D integration has been a promising packaging approach intrinsically underpinning heterogeneous integration. The physical proximity of diverse components (e.g., chiplets) on interposers entails multi-physics, including thermal coupling, which affects the performance and reliability of the entire system. Consequently, interposer-level thermal monitoring is required to avoid overheating during run-time. Furthermore, reusable interposers have also recently been proposed in the literature, implying that a specific interposer is used for multiple systems. Therefore, conventional thermal sensor placement methods, developed for a specific system, are incompatible with this emerging design concept. A new flow focusing on thermal sensor allocation and thermal map reconstruction for reusable interposers is proposed. The flow utilizes a transformer neural network to reconstruct the thermal map of the interposer and hyperparameter tuning to select the appropriate thermal sensor locations that minimize the reconstruction error across the entire set of available floorplans for a specific transformer architecture. The benchmarks used to train the transformer are produced through gem5, McPat, HotSpot and TAP-2.5D for ten different floorplans, showcasing the effectiveness and generality of the approach compared with prior art and achieving an average maximum error of less than 1K.
Reducing the precision in post-training quantization can cause catastrophic accuracy loss in Deep Neural Networks, especially when compressing the activations. To address this problem, we present a novel adaptive-precision quantization (APQ) and accelerator design that achieves lossless activation compression by exploiting the inherent coding redundancy. Compared to existing APQ methods, this design can be generalized to implement asymmetric quantization, making it particularly suitable for activations. The accelerator offers a practical solution to mitigate the computational workload imbalance problem incurred by variable precision. A dual-precision quantization scheme further provides the flexibility to trade off accuracy and performance.
The growing need for advanced memory architectures leveraging 3D integration has become increasingly critical in modern computing systems. In particular, memory architectures that match the performance of static random access memory (SRAM) while significantly increasing density are highly impactful. In this paper, we propose a 3D integration-based hybrid InGaZnO(IGZO)/Si embedded dynamic random access memory architecture (Hybrid-3D) and circuit design, which markedly increases on-chip memory density and enhances system performance. The superiority of Hybrid-3D is demonstrated through rigorous validation involving process integration verification, transistor-level modeling, and circuit-level memory design. Detailed evaluations of the vertically stacked memory operation confirm stable operations, enabling a 22× increase in on-chip memory density compared to SRAM. Integrating Hybrid-3D on-chip memory into neural processing unit (NPU) architectures results in substantial improvements in energy efficiency and processing speed. System-level evaluations across vision and natural language processing (NLP) tasks reveal a maximum energy efficiency improvement of 3.2× and a throughput increase of 2.6×.
Point cloud diffusion models, as an emerging 3D generation method, hold broad prospects in 3D modeling, AR/VR, and so on. However, their reliance on costly full-precision neural network computations during extended denoising process limits their practical application. To address this challenge, we propose RAPID, an accelerator co-designed with a space-aware quantization method. First, RAPID uses K-means to partition points into groups and computes scaling factors in each, mitigating accuracy issues caused by uneven distribution. Second, it employs a mixed-precision quantization scheme that uses low precision for internal point groups and high precision for detail-rich edge groups, ensuring generation quality while minimizing bit-width. Third, it reuses computation results for groups with little change between timesteps, reducing redundant calculations. Moreover, RAPID’s hardware features a mixed-precision PE array for efficient computations at various bit-widths, and a filter for dynamic bit-width allocation and result reuse. Evaluations show that, compared to the NVIDIA RTX A5000 GPU and state-of-the-art accelerators, RAPID achieves average speedups of 9.22×, 4.66×, 3.69×, and 3.01×, and energy savings of 61.74×, 4.30×, 3.94×, and 2.76×, with negligible accuracy loss.
Preventing unexpected long-latency spikes is crucial for latency-sensitive hardware systems like Solid-State Drives (SSDs). Conventional test case (TC) generation methods often lack reproducibility and rely on proprietary internal firmware knowledge, limiting their applicability. To address this, we propose SNIFFER, a vendor-agnostic, black-box framework that utilizes Reinforcement Learning (RL) for the automated generation of latency anomaly-inducing TCs. SNIFFER interacts directly with real SSD hardware, using only externally observable metrics from standardized tools like Flexible I/O and Open Compute Project. Our framework formulates the problem as a sequential decision-making process, enabling an RL agent to learn complex I/O patterns that induce stress. We demonstrate that SNIFFER consistently generates effective TCs, inducing up to 74.7% higher maximum latency in up to 85% fewer steps compared to a random baseline. More importantly, we demonstrate its superiority over alternative black-box optimization methods, such as Genetic Algorithms, validating our approach for non-stationary hardware environments. SNIFFER ’s ability to reproducibly generate diverse and stressful TCs makes it a powerful tool for automated industrial validation pipelines.
The vertical integration of 3D ICs introduces physical design complexities beyond those of conventional 2D ICs, especially in the multi-tier placement stage. Existing pseudo-3D design flows typically follow a sequential process of 2D placement followed by tier partitioning, which focuses on balancing cell distribution across tiers but largely overlooks timing-related factors. In this paper, we propose a timing-driven 3D IC placement framework that explicitly prioritizes critical paths throughout the placement process. Starting from an initial 2D placement, we apply an ILP-based tier assignment that encourages critical-path cells to reside on the same tier, reducing unnecessary vertical transitions that degrade timing. We then perform critical-path-aware planar refinement, where the locations of critical-path cells are iteratively adjusted toward path-centric targets, with displacement magnitudes determined by timing criticality. Finally, tier partitioning for non-critical cells is conducted using an enhanced cost function that minimizes interference with previously optimized critical paths, thereby preventing relocation during subsequent legalization. Experimental results demonstrate 13.0% improvement in worst negative slack (WNS) and 7.85% reduction in total negative slack (TNS), validating the effectiveness of our critical path-driven placement strategy.
Modern computing systems increasingly feature diverse co-running workloads with varying memory access patterns and requirements. However, existing main memory architectures employ rigid, application-agnostic memory mapping strategies, leaving significant performance potential untapped. This paper introduces MemoryIslands, a novel methodology for treating main memory as a federated collection of independent regions, or "islands," each tailored to the unique memory demands of individual applications. Our contributions include: (1) a profiling-based methodology to identify optimal address mappings for diverse workloads and (2) a software-aware hardware co-design approach that configures memory controllers to leverage these islands without requiring changes to the software-hardware interface. Evaluation across over 80 workloads on single- and multi-core systems demonstrates significant performance improvements—up to 50%—compared to state-of-the-art static mapping techniques. By enabling application-specific memory mappings and partitioning, MemoryIslands provides a scalable and efficient solution to address the limitations of existing memory architectures.
Scaling up the number of qubits in fault-tolerant quantum computing calls for scalable multiplexed control and schemes. This paper introduces a novel digital code multiplexing approach for charge readout in quantum computing. Based on digital control and demodulation, the proposed scheme eliminates the need for sinusoidal or more complex waveform generation. Unlike conventional reflectometry, where the number of qubits dictates the number of physical resonant circuits, the proposed method only depends on digital clock frequency and target readout time, enabling a more compact and scalable implementation. This work demonstrates the proposed scheme by modulating two single-electron transistors (SETs) through a transimpedance amplifier (TIA)-based readout chain operating at 4.2 K. Experimental results show that the proposed method reliably distinguishes SET conductivity states under multiplexing, achieving a bit-error rate (BER) below 10−3 within an integration time of 4.55 µs.
