This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from $\mathbf{1} \boldsymbol{\mu} \mathbf{A}$ to $\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at $\boldsymbol{I}_{\text {out }}$ of $100 \mu ~\mathrm{A}$ and $300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents a summary of the commonly used inductive DC-DC voltage converters (VCs) for step-up (boost) voltage conversion with their key characteristics. Many of these topologies are based on conventional Buck and Boost converters with different alterations and/or additional components. The analysis includes current conduction modes, input source and output capacitor current stresses, and the conversion ratio under Continuous Conduction Mode (CCM) operation. The selection of VCs considered in this study was guided by the feasibility of future full on-chip integration, leading to the exclusion of topologies exhibiting excessive complexity, requiring more than two inductors or need of transformers. This overview summarizes the key characteristics of the selected circuits and provides a guide for the further design of inductive voltage converters.

This article introduces the design and analysis of a slope detection circuit tailored for on-chip sensing of the load current in DC-DC converters. The novel indirect sensing approach is grounded in measuring the output voltage slope across the filtering capacitor during discharge phases. Consequently, this slope data can be effectively harnessed to control the converter switches. The slope detector circuit was designed in standard 65 nm CMOS technology using the nominal supply voltage of 1.2 V and can be used for current sensing within the range from one to hundreds of mA. Since the proposed circuit has mainly digital character, the robustness to process, temperature and supply voltage variations can be ensured rather conveniently.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

This work deals with different simulation configurations for verifying the function of a one-time digitally calibrated fully-differential difference amplifier (FDDA) designed in 130nm CMOS technology. In terms of calibration, the compensated parameter is in this case, the input offset voltage $V_{IN_{-}OFF}\cdot$ Specific FDDA configurations based on open (OL) and closed (CL) feedback loops are presented here for simulation of parameters such as frequency and phase responses, $V_{IN_{-}OFF}$, CMRR and PSRR parameters. Individual simulation configurations are divided into universal (precalibration) and post-calibration ones. In the case of CL, the effect of small-signal output resistance of the FDDA on its DC gain is analyzed through circuit model, which has to be considered in the low-voltage design.

This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements.

This paper presents a workplace for practical implementation of Maximum Power Point Tracking (MPPT) algorithms and means for comparison of their efficiency that is critical for efficient and reliable power conversion by solar cells as well as for the whole voltage conversion (VC) system. This is available by providing an option for implementation of various MPPT algorithms to Field Programmable Gate Array (FPGA) board that are designed in Hardware Description Languages (HDL). MPPT algorithms are created for utilizing the Pulse Frequency Modulation (PFM) control loop of a fully integrated DC-DC voltage converter based on high frequency switching of on-chip inductor with Photovoltaic (PV) cell as a power source for Energy Harvesting (EH) system. The whole VC system was created in standard 65 nm CMOS technology. In addition, two MPPT algorithms were created based on Perturb and Observe (P&O) method and implemented on the chip.

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

This paper presents a design and analysis of the slope detection circuit for on-chip sensing of load current in DC-DC converters. The proposed indirect sensing approach is based on measurement of the output voltage slope across the filtering capacitor during the discharging phase. Thus, information about the slope of output voltage can be further used for rather effective control of switches in the converter. The slope detector circuit was designed in standard 65 nm CMOS technology using the nominal supply voltage of 1.2 V and can be used for current sensing within the range from one to hundreds of $\mathbf{mA}$ . Since the proposed circuit has mainly digital character, the robustness to process, temperature and supply voltage variations can be ensured rather conveniently.

This paper presents an overview and State-of-the-Art of fully integrated inductors with common fabrication processes used for implementation of these structures into a chip. The first step is an overview of fabrication technologies that starts with standard CMOS general purpose processes expanded by Far-BEOL and substrate alteration process (SOI, Silicon Embedded, TSV, TGV, PTH, Core Insertion); and continues to advanced process nodes like SMMT and Bond Wire utilization. Then, an overview of fully integrated inductor structures consists of selected topologies with notable parameters achieved in last few years. Critical parameters of integrated inductors include: inductance L DC , inductance density LA, quality factor Q, self-resonant frequency FSR and series resistance R DC . These parameters are as important as the purpose and fabrication process.

The paper describes design and analysis of a Low-Dropout Regulator (LDO) with a high value of the power supply rejection (PSR) at high frequencies (above 10MHz). The proposed LDO was designed in a standard 65 nm CMOS technology. The output of the designed LDO can be adjusted by the voltage reference used in the LDO. The obtained results prove a very good PSR parameter at frequencies above 10 MHz, where the value of -40 dB is observed in the worst case. Additionally, the designed LDO topology exhibits promising load regulation properties even for a low value of the output capacitor. The proposed LDO can be fully integrated on a chip, and used in complex switching converter Systems on-Chip (SoC), where a high value of PSR is required.

In this work, we propose fully integrated multi-layer stacked topology of asymmetrical inductor with patterned ground shield (PGS), which also serves as capacitor. The main aim of the study is efficient usage of limited chip area for integrated passive components by challenging layout properties of asymmetrical integrated inductor and integrated MOS capacitor and enhancing their main electrical properties. Several principles of geometry modifications(vertical and horizontal parallelization, slicing, tapering, equal path lengths) were applied to a four-turn octagonal asymmetrical integrated inductor with the series DC resistance $R_{L}= 1.75\Omega$ and inductance $L=11.66 nH$ on low frequencies. Remaining area under integrated inductor was used for a capacitor with capacitance $C_{PGS}= 1.6 nF$ and the equivalent series resistance $R_{C}= 7.25\Omega$ . The whole structure was designed in a standard 65nm CMOS technology for use in a switched DC-DC power converter working in MHz-range for a Photovoltaic (PV) Energy Harvester (EH).

This paper is focused on the design of digital electronics using Field Programmable Gate Arrays (FPGA) that can be easily applicable to school education process. At the beginning, paper is aimed at comparison of digital and analog electrical signals, and a brief introduction to digital electronics. The next section addresses an introduction and brief characterization of FPGA board Basys3. This board is suitable for education purposes as a teaching aid for students who would like to test their gained skills in hardware description languages or school subjects focused on the digital circuits design. Then, the design flow for digital circuits using Vivado design environment is described. The final section concludes the paper.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

This paper essentially deals with the technique of digital autocalibration of analog integrated circuits (IC), specifically the voltage reference circuit. The work describes general meaning and purpose of IC digital calibration approach. An applicable concept of digitally autocalibrated voltage reference with the output voltage value of 96 mV is presented. The accuracy depends mainly on the fluctuation of parameters of individual transistors, which is caused by the imperfections of the production process itself. Within the presented concept, there is introduced a specific principle of autocalibration, where the main purpose is to suppress the influence of the boundary conditions of the technology.

This paper offers basic knowledge about the Fourier and Laplace transforms shown through graphical interpretation. Mathematical and graphical comparisons between the Fourier and Laplace transforms are presented in general form and also on a specific example. It describes the definition of the both transforms and clarifies the Region of convergence (ROC) of the Laplace transform. Based on these fac...

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.

The main goal of this work is to visualize one of the basic properties of the Sigma-Delta analog-to-digital converter (Σ-Δ ADC) - noise shaping. For this purpose, two models of the Σ-Δ modulator were analysed - the model using an integrator without delay and the model using an integrator with delay. Both of these visualizations are based on the principle of superposition, since two input signals (the useful input signal and the quantization noise) are considered in the models. Visualizations are shown in the z-plane as well as using the magnitude vs normalized frequency graphs constructed in Matlab environment.

In this paper design and function of the fully differential (FD) switched-capacitor (SC) integrator for ultra-low voltage Sigma-Delta analog to digital converter (Σ-Δ ADC) are presented. The proposed integrator was designed for differential input signal and applicable as a main analog block of ultra-low voltage Σ-Δ ADC in standard 130 nm CMOS technology. The main block of proposed integrator is operational transconductance amplifier (OTA) based on two-stage Rail-to-Rail (RtR) FD operational amplifier (OPAMP) working in sub-threshold regime. The characteristic properties of this circuit is non-standard OTA topology, using SC common-mode feedback (CMFB) circuit and using switching T-gates. All of these subcircuits are supplied by only 0.6 V with achieved gain 24.09 dB and cutoff frequency 165.95 kHz.