This paper presents a high-performance, fully integrated inverter-based low-dropout (LDO) voltage regulator incorporating a dedicated Transient Overshoot/Undershoot Suppression (TOS) circuit for advanced on-chip power management. Implemented in 180 nm CMOS technology, the proposed LDO operates over an input voltage range of 0.9-1.4 V and an output voltage range of 0.8-1.3 V, delivering up to 150 mA of load current with a quiescent current of 9-303 μA. The TOS circuit operates by sensing rapid output voltage excursions through coupling capacitors (Cm3, Cm4) and activating a low-resistance discharge/charge path via switch transistor M21, thereby correcting output deviations very quickly without affecting steady-state regulation. High-speed operation and complete integration are made possible by a small 40 pF output capacitor. The simulation findings show a PSRR of 45.6 dB at 10 kHz, a settling time of 81 ns with a step edge of 10 ns, and a low output voltage variation of 94 mV at 149 mA load transition. The suggested structure produces superior figures of merit (FoM1 = 0.069 mV, FoM2 = 0.019 ps) when compared to state-of-the-art designs, confirming the effectiveness of the TOS circuit and the inverter-based architecture for sophisticated on-chip power control.
In this paper, a high-precision and low-offset mixed-signal analog front-end (AFE) architecture for industrial sensor interfaces is proposed. The analog amplification stage employs a current-feedback programmable gain instrumentation amplifier (PGIA) combining chopper stabilization and a successive approximation register (SAR) logic-based automatic offset calibration loop (AOCL) to effectively suppress low-frequency noise and eliminate residual offset voltage. For high-resolution signal digitization, a 2-1 multi-stage noise-shaping (MASH) sigma-delta analog-to-digital converter (ADC) is utilized, followed by a fourth-order cascaded integrator-comb (CIC) digital filter with an oversampling ratio of 512. The proposed circuit is designed and simulated using the Spectre tool in the Cadence environment based on a 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) process with a 1.8 V power supply. Simulation results demonstrate that the PGIA achieves an input offset voltage as low as 100 nV and an equivalent input noise power spectral density of 22.2nV/Hz at 1 kHz, with the gain error strictly controlled within 0.001%. Furthermore, the ADC attains an effective number of bits (ENOB) of 15.46 bits, a signal-to-noise ratio (SNR) of 94.85 dB, and a competitive spurious-free dynamic range (SFDR) of 100.05 dBc, validating its suitability and accuracy for high-precision measurement applications.
Radiation-hardened latches play a critical role in modern digital integrated circuits by mitigating radiation-induced soft errors. However, the redundant feedback structures commonly employed in these latches tend to obscure manufacturing defects, resulting in degraded testability and reduced yield. Scan-test-aware hardened latches, such as STAHL and HIDER, have been proposed to improve defect coverage during scan testing. Nevertheless, these designs still suffer from inherent limitations, including increased propagation delay, while the STAHL design lacks self-recovery capability under single-node upsets (SNUs). This paper proposes a low-power, scan-test-aware radiation-hardened latch, termed LATHE, which supports self-recovery from arbitrary SNUs. The proposed latch employs design-for-test (DFT) principles and achieves a high defect coverage. Simulation results using the 32 nm PTM technology model show that LATHE achieves 83.93% defect coverage. In addition, the proposed latch demonstrates robust self-recovery under SNU conditions and maintains stable operation across process, voltage, and temperature (PVT) variations. Compared with representative designs, LATHE reduces propagation delay, power consumption, and power–delay product (PDP) by 77.62%, 55.56%, and 93.88%, respectively. These results indicate that LATHE provides an effective trade-off among reliability, testability, and performance.
This paper presents HEAFS, a hardware-efficient approximate FP16 floating-point square-root architecture tailored for fast and energy-aware edge applications, including signal processing and machine-learning workloads. HEAFS employs a streamlined approximation strategy that reduces datapath complexity while preserving high numerical fidelity. FPGA synthesis on an Artix-7 device demonstrates notable improvements over existing multiplier-free designs, with HEAFS requiring the least hardware resources and achieving reduced dynamic power, critical-path delay, and power–delay product (PDP) among the evaluated architectures. In addition, ASIC synthesis at 90 nm technology further confirms reductions in cell area, power consumption, and propagation delay, supporting its suitability for compact VLSI implementations. Despite its reduced hardware footprint, HEAFS maintains accuracy comparable to high-precision cluster-based designs while achieving up to 82% reduction in hardware utilization and 67% reduction in PDP. Comprehensive analytical and graphical evaluations confirm stable approximation characteristics of HEAFS across the complete input domain. Figures of Merit (FoM), combining accuracy and energy-efficiency indicators, demonstrate that HEAFS provides a favorable trade-off between numerical performance and implementation cost relative to existing architectures. The practical effectiveness of HEAFS is further validated through representative application studies, including Sobel-based edge detection, K-means-based color quantization, and RMS computation for signal-processing workloads, where it preserves output quality while reducing hardware and energy requirements. Overall, HEAFS achieves an effective balance between computational accuracy and implementation efficiency, providing a compact and energy-aware approximate square-root solution suitable for FPGA and ASIC deployment in edge computing, imaging, and machine-learning systems.
Detecting and correcting adjacent errors has become important in memory systems using high-density DRAM chips. The reason is that, in these systems, a strike by an energetic particle can upset one or more adjacent bits. In this paper, we present a simple solution for this problem based on integer codes capable of correcting/detecting burst errors within one byte and detecting double errors. Unlike the standard approach, in which the encoder/decoder is realized as a dedicated hardware block within the DRAM controller, the proposed method uses the processor as both the encoder and decoder. The effectiveness of this solution is demonstrated on a theoretical model of an eight-core processor. The obtained results show that the proposed method introduces a delay that is negligible compared to DRAM access latency, while enabling flexibility that is not achievable with conventional hardware-based solutions.
Analog circuits are indispensable in modern electronics, yet their design heavily relies on manual expertise, especially in transistor sizing. Despite long-standing research efforts, it is still challenging to achieve robust and efficient analog design automation. Recently, there is a growing interest to address above mentioned challenge via artificial intelligence methods such as genetic algorithm (GA) and deep reinforcement learning (DRL). Following this trend, a novel GA-enhanced deep reinforcement learning framework is proposed in this work for analog circuit design automation, which accelerates policy convergence during searching the design space according to the Pareto fronts oriented starting points collected by non-dominated sorting GA (NSGA). Feasibility of the proposed method is demonstrated via sizing typical amplifiers in terms of superior performance, efficiency and solution robustness.
Through-Silicon Vias (TSVs) are the key component in stacking three-dimensional chips. It is imperative to detect TSV faults during the manufacturing process. However, the high testing cost and difficulties in testing the entire TSV bonding process using the same structure are open challenges in the manufacturing process. This paper proposes a TSV testing procedure based on a reconfigurable ring oscillator structure. The reconfigurable ring oscillator (RRO) performs fault detection on TSVs Pre-bonding and carries out Mid-bond and Post-bond testing by reusing the technique Pre-bonding. The reconfigurable Linear-feedback shift register(RLFSR) can be employed for circuit testing and generate RRO control signals. Our simulation results of HSPICE substantiate that the proposed structure effectively detects faults at each stage of TSVs. Compared with the state-of-the-art testing techniques, the test data storage volume is reduced by 53.41% and 24.39%, respectively, and the area overhead is reduced by 42.33% and 19.87%, respectively.
This paper presents a half-select disturb-free 11T (HF11T) SRAM cell using a single bitline to improve read/write speed, provide high stability, consume low power, and offer a better Ion/Ioff ratio. The integration of the proposed SRAM cell with bit-interleaving architectures and error correction coding significantly improves its soft-error immunity. It is compared with several state of the art designs, including a half-select free single-ended 10T SRAM (HSSE10T), a single-ended HS free 11T SRAM (SEHF11T), a Schmitt trigger 11T SRAM (ST11T), and a half-select disturb free 11T SRAM (HSDF11T) cells, using Cadence Virtuoso 45 nm CMOS technology at 1.2V supply voltage. It exhibits 12.74 and 3.37 times less read delay (TRA) and write delay (TWA), respectively, compared to other SRAM cells. It has enhanced stability with 1.15, 2.24, and 2.50 times improvements in read and hold SNM (static noise margin), and write noise margin (WNM), respectively, compared to other SRAM cells. It shows a maximum reduction of 1.89 and 1.45 times leakage power and dynamic power consumption, respectively, compared to other SRAM cells. Another notable advantage is that the HF11T cell achieves an Ion/Ioff ratio more than 2.5 times higher than the competing SRAM designs. The consistency of this improvement is demonstrated through extensive Monte Carlo (MC) simulations.
This paper presents an area-efficient hardware architecture for an 8-point approximate Discrete Cosine Transform (DCT) for JPEG compression: the focus is on the digital-circuit realization of a signal-processing kernel for embedded imaging. As its transform kernel the design adopts the angle-minimized approximation matrix T1 of Oliveira et al. whose coefficients lie in {0,±1,±2}, so that all multiplications can be replaced by shift-and-add operations. The resulting design employs a 5-stage pipeline that computes the complete 2D-DCT/IDCT in 25 clock cycles, using 76 adders and 56 bit-shift operations with zero hardware multipliers. Functional verification uses ModelSim RTL simulation; the mapped design is further validated on FPGA against a Python golden reference. Image-quality evaluation on 210 grayscale images (512 × 512) drawn from the USC-SIPI Image Database, under a JPEG encode flow, yields an average Peak Signal-to-Noise Ratio (PSNR) of 34.81 dB and a Structural Similarity Index (SSIM) of 0.951 relative to the exact-DCT JPEG reference. Synthesis on Virtex-7 XC7VX330T reports 1,810/2,192 LUT usage (2D-DCT/2D-IDCT) and 914/915 Mpixel/s latency-based throughput, and in-system verification is performed on the Kintex-7 XC7K325T FPGA. ASIC synthesis on the FreePDK45 45 nm standard-cell library yields Fmax=1.72 GHz with a 19,000-gate equivalent area (20258μm2) and 0.05 W dynamic power for the standalone 1D core.
FPGA-based TRNGs suffer from the environmental vulnerability of physical entropy sources and excessive hardware overhead of conventional post-processing. To address the demand for high-security entropy generation on resource-constrained IoT nodes, this paper presents a lightweight TRNG featuring a deep coupling of hybrid entropy sources and a nonlinear fusion engine based on two-dimensional mixed-chaotic system (2D-MCS). The proposed architecture employs an asymmetric 2D-MCS as the main-path engine for entropy fusion and conditioning, eliminating independent post-processing modules. By dynamically mapping logic jitter and low-bit uncertainty from the XADC to the perturbation and sampling-modulation paths, the architecture achieves efficient entropy accumulation and redistribution with minimal resource and power consumption. The experimental results on FPGA platforms demonstrate that the proposed TRNG achieves a theoretical average throughput of 64.0 Mbps at 100 MHz and features dynamic speed stabilization. The entropy source failure tests confirm that the system demonstrates strong fault tolerance under single-source failure scenarios.
In intelligent FPGA design flows, CNN-based multi-task learning models predict non-timing metrics from image-like data, while GNN-based models handle graph-like data for timing metrics. Despite the interdependence between these metrics, existing joint prediction models are exclusively GNN-based, limiting them to graph-like data processing. To overcome this, our paper proposes a novel approach that simultaneously predicts timing (critical path delay) and non-timing metrics (congestion, wirelength, power) by processing both graph-like and image-like data. This co-prediction is framed as a multi-modal multi-task learning problem. We introduce MMNet, a multi-modal multi-task learning model that integrates CNN and GNN trunks with hard+cascaded information sharing, inter-hybrid trunk information fusion, and a geometric loss strategy. MMNet has three variations based on the fusion mechanism: MMNet-CC (concatenation), MMNet-CS (cross-stitch), and MMNet-CA (cross-attention). Cross-design experiments on various FPGA designs demonstrate MMNet’s superior prediction performance and time efficiency over baseline models. MMNet-CC proves most effective and efficient, followed by the robust and second-fastest MMNet-CS, while MMNet-CA performs worst. Ablation studies confirm the critical contributions of the hard+cascaded information-sharing mechanism, the geometric loss strategy, the residual connections within the CPD-specific trunk, the individual image-like features, and the combined use of both image-like and graph-like features in enhancing MMNet’s predictive performance.
Analog integrated circuit (IC) design involves high-dimensional design spaces, strong nonlinearities, and conflicting performance objectives. While machine learning has shown promise, achieving accurate performance modeling and reducing the cost of repeated circuit simulations remain major challenges. This paper presents a hybrid optimization framework that integrates deep reinforcement learning (DRL) with physics-aware techniques for multi-objective analog IC netlist optimization. A physics-aware gm/ID predictor is incorporated to improve model accuracy, while a gm/ID-guided filtering strategy accelerates design space exploration by screening out low-potential candidates early. The DRL agent effectively drives multi-objective optimization across performance metrics. Evaluations on eight analog circuits from four categories, using the open-source SKY130 PDK, demonstrate that the proposed framework improves key performance metrics by up to 70.81% on average and reduces runtime by approximately 21.61% compared to baseline methods. Ablation studies confirm the individual contributions of the performance prediction and acceleration modules in enhancing efficiency and solution quality.
With the rising demand for voice-activated devices in the internet of things (IoT), optimizing keyword spotting (KWS) for minimal latency, power, and hardware cost remains a critical challenge. This paper introduces EchoChat, an intelligent system-on-chip (SoC) featuring an ultra-low latency, low-power KWS accelerator tailored for real-time voice interaction. We apply multi-dimensional optimizations to a lightweight KWS model, achieving a 98.3% reduction in memory usage and a 98.2% improvement in computation speed. Customized computations in the accelerator, including pipelining, sparsity, approximation, and aggressive diagonal computation, further boost efficiency. Post-layout simulations in a 40 nm CMOS process show that the KWS accelerator achieves 2.98 ms latency, 28.33 μW power consumption, and 0.28 mm2 area. Compared with cutting-edge works, the accelerator provides a compact area and low latency. The EchoChat, with a compact 1.34 mm2 footprint, delivers competitive performance among other IoT-oriented audio SoCs. Demonstrated on an FPGA prototype, EchoChat represents a significant advancement in energy-efficient, real-time voice processing, paving the way for smarter and more responsive embedded systems.
To improve the conversion efficiency of gallium nitride (GaN) device based DC-DC converter and reduce the shoot-through risk of the high-side and low-side GaN devices, an adaptive dead time control circuit for the GaN device based DC-DC converter is proposed in this paper. A digital control cycle-to-cycle (DCCC) technique based on the combination of a variable delay module and a fixed delay module is used in the circuit. Based on the unique judgment and control methods in the proposed technique, the circuit can achieve adaptive adjustment and approach the optimal dead time value. By adopting a novel voltage reduction circuit, the process feasibility of voltage reduction sampling at switch nodes is improved, and the fast response requirement for dynamic change is satisfied. The 0.18 μm BCD process and the EPC2014C GaN power transistor are adopted to fabricate a buck DC-DC converter for measurement and verification. The measurement results show that under the conditions of 40 V input voltage, 5 V output voltage, 5 A load current, and 6 MHz switching frequency, the circuit exhibits a turn-on dead time Tdead_on of 320 ps, and a turn-off dead time Tdead_off of 420 ps. The peak efficiency of the proposed adaptive dead time control converter is 90.6%, which is 3.9% higher than the fixed dead time control scheme. The proposed adaptive dead time control circuit possesses the advantages of low dead time and high efficiency.
