A new method for extracting the area, peripheral and corner capacitance components of bipolar junction transistor, using measurements versus bias on a number of different structures is presented and validated. The same model with different parameters is used for the three components. Validation has been made using a quasi-2D simulator. Finally, it is shown that this method gives accurate results regarding the goodness of fit

A one micron bipolar process using trench isolation and polysilicon emitter has been evaluated and characterised. The demonstration of yield was achieved on a 10000 gate VLSI circuit.