A 1.2¿m mixed analog-digital BICMOS technology has been developed and characterized, The objective of this technology is to achieve simultaneously high density CMOS logic (5V) and high performance bipolar transistors for analog applications (12V). High speed NPN and vertical PNP have, been implemented for high voltage requirements, together with the need of high frequency performance. Finally the performance of the technology is demonstrated on a RGB decoder circuit, for IDTV applications.

A 54MHz video restitution circuit fabricated in a high-performance 1.2um BiCMOS technology called HF3CMOS is described. The circuit receives two 8bit busses (Luminance Y and Chrominance CrCb signals) each at 27 Megasamples/second and provides on its outputs 3 analog signals either R,G and B or Y, Cr and Cb. Provision is also made for an analog multiplexing between the outputs of the internal DAC and external analog RGB signals. Chapter II gives a description of the circuit. Design options choosen for its realisation are discussed in Chapter III. Chapter IV briefly describes the technology used. Measurement results are discussed in Chapter V.

A quad 512-b static shift register consuming 1.8 mW/stage designed to demonstrate the capabilities of an advanced bipolar silicon technology is discussed. The process uses 1- mu m lithography, trench isolation, polyemitter transistors, polysilicon resistors, and polycide layer for local interconnections. This VLSI circuit (over 35 K transistors, 86-mm/sup 2/ chip) has been implemented on a sea-of-cells structure. An appropriate scheme has been used for the clock distribution. The experimental results show operation at a clock frequency up to 950 MHz.< >

A one micron bipolar process using trench isolation and polysilicon emitter has been evaluated and characterised. The demonstration of yield was achieved on a 10000 gate VLSI circuit.