In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 μm-diameter in this 3D EPIC packaging. A 750 Ω-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radioover-fiber (ROF) solutions.

We demonstrate a 2.5D silicon optical interposer for the integration of multi-channel optical transceiver (TRx) operating at 50 Gbps/ch and more. It completes optical transceiver by flip-chip bonding the photonic ICs (PIC) such as Mach-Zehnder modulator (MZM) and Germanium-photodetector (Ge-PD), and electronic ICs (EIC) such as modulator driver and trans-impedance amplifier (TIA). In this study daisy chains of PICs and EICs are flip-chip bonded using wafer-level fabricated Cu-pillar μ-bumps. The optimally designed transmission line on the interposer shows insertion loss (S21) less than 1.5dB up to 50 GHz for the length of 8 mm. For the transmitter (Tx) packaged with PICs and EICs whose transmission line length is two times longer than that of packaged Rx shows less than 10dB of insertion loss up to 50 GHz. The packaged Tx successfully demonstrates eye diagram at 50 Gbps. Total data rate can increase to 400 Gbps and 800 Gbps and more by increasing the channel numbers.

Glass substrate has advantages of lower cost and lower RF loss compared with high resistivity Si substrate, but there is a challenge within process fabrication by the conventional CMOS fabrication system because of wafer transparency. Temporary bonding and de-bonding technology was used within process development. Transmission line was designed and fabricated on the glass substrate after process optimization.

100 Gbps (4 × 25 Gbps) optical receiver (Rx) module is demonstrated using Germanium (Ge) photodetector (PD) which is fabricated through Silicon-photonics process using 750 ohm-cm of high-resistivity silicon oxide insulator (SOI) wafer. Trans-impedance amplifier (TIA) and Ge PD are packaged with chip-on-board (COB) manner on a printed circuit board (PCB). High speed PCB for the assembly of both electronic and photonic devices in COB package is precisely designed from the material selection to the device footprint layout and transmission line design. The layout on PCB is optimized using high frequency simulation tool of HFSS to minimize RF loss happening in the transmission line and electrical interconnection points of bond wires. Electrical-optical (EO) S-parameter measurement for the Ge PD shows 22 GHz of transmittance (S21) 3dB bandwidth. Photocurrents of the photodetector induced by the optical input power are analyzed for signal integrity both TIA ON and OFF states. Photocurrent changes by the misalignment of the lensed optical fiber coupled to the edge coupler of the Ge PD shows that 3dB misalignment tolerances are 5.5 µm in the longitudinal and around +/-1 µm in the lateral directions. This COB packaging technique of optical Rx module can be applied for the integration and assembly of the optical module of higher data rate of 100 Gbps and beyond.

High-speed optical module is demonstrated using silicon photonics integrated circuits (Si-PIC) by compact packaging on ceramic submount of which size is 4 mm x 21 mm x 1.1 mm. The electronic integrated circuits (EIC) such as transimpedance amplifier (TIA) for photodetector and driver IC for modulator are flip-chip bonded on the submount using 1 mil diameter of Au stud bumps. The optical transceiver is packaged through the flip-chip bonding of the packaged submount by SAC solders on the evaluation PCB on which RF signal transmission lines are precisely designed. The reliable flip-chip bonding state of the EICs and submount are verified through shear test and x-ray image. Eye diagram is demonstrated at 20 Gbps for receiver module.

We extend the short-reach dynamic range of 10-Gb/s silicon photonic receiver to long-reach by changing reverse-bias of Ge-PD to adopt to input power. PD is in CMOS SOI and the electronics is in 40nm CMOS.

On-chip RF loss management is a critical issue for the packaging of the silicon photonics ICs (Si-PIC) determining signal integrity of both devices and systems. In this paper, we present optimal condition of on-chip transmission lines (TLs) for Si-PIC based on SOI wafer. Optimal on-chip 3dB-loss length is studied and crosstalk is analyzed for the multichannel TLs. The 3dB length is calculated to be 8~10 mm, and adjacent channel crosstalk becomes less than -20dB when the channel separation is larger than 2 times of the TL width.

We demonstrate chip-on-board (COB) packaged optical module operating at data rate of 25 Gb/s based on silicon photonic integrated circuits (Si-PIC). Electrical loss and packaging criteria for high-speed data transmission in COB packaging is discussed.