Intrinsic gate oxide reliability of silicon carbide (SiC) power MOSFETs has improved significantly over the years. Nonetheless, to achieve a level of overall reliability comparable to Si devices, it is essential to address extrinsic defects that could introduce early life failures in the gate oxide of SiC devices. Gate screening can be performed to eliminate these early life failures; however, proper optimization of screening methodology is required to maximize the useful life of the devices while maintaining a low failure rate and avoiding potential adverse effects, such as threshold voltage instability, due to the high gate stress during screening. In this paper, we demonstrate enhanced intrinsic and extrinsic reliability of gate oxide across two distinct wafer fabrication facilities, achieved through optimized processing and screening methodologies.

This paper discusses gate oxide reliability in SiC vertical power MOSFETs under gate and drain bias stresses. Excellent intrinsic and extrinsic reliability has been achieved via optimized processing and screening methodologies. Time-dependent dielectric breakdown (TDDB) and accelerated reverse bias (ARB) tests demonstrate that the reliability of the gate oxide in SiC MOSFETs is comparable to that of silicon devices.

This work presents power cycling test results from Wolfspeed 1200V 75mO SiC discrete MOSFETs in TO-247-4L package. The results are used to adjust the parameters of a previously reported model. The model parameters thus derived show that the model matches the data collected and agrees with the general trend seen in literature for similar devices. This study captures a broad range of test parameters: temperature swings (maximum minus minimum junction temperature during a test) between 30K and 100K, device on-time, t(on), between 0.01s to 2s, and maximum junction temperature between 115°C to 180°C. This model has been successfully applied to various industrial mission profiles to predict the lifetime of SiC MOSFETs in the field to help design for higher reliability.

At high gate bias it has been shown that SiO2 will undergo impact ionization resulting in hole generation, the onset being oxide thickness and temperature dependent. The generated holes tend to be trapped in SiO2, significantly shifting the threshold voltage and affecting the gate failure under TDDB stress. The results presented here set important limits regarding gate fields and temperatures for TDDB stress levels and oxide lifetime predictions, gate screening conditions, and high voltage gate testing.

Robustness under reverse bias is a pivotal reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, typically involving multiple VDS stress values beyond the rated drain bias but below the avalanche voltage, is deemed optimal for assessing the device lifetime in the blocking mode. However, generating adequate failure statistics within a feasible timeframe during ARB tests can be arduous, particularly for devices engineered to undergo avalanche breakdown at lower drain voltages than those necessary to induce gate oxide wear-out failures within a reasonable time. This paper presents an innovative, streamlined alternative modeling approach, where qualification-like high temperature reverse bias (HTRB) or ARB test at a singular stress voltage for a suitable stress duration can be utilized to predict gate oxide lifetimes under blocking conditions, obviating the need for any prolonged testing.

Gate oxide reliability is a challenge in SiC MOSFETs particularly due to the presence of high electric field in the dielectric during device operation and blocking, and SiC/SiO 2 interfaces suffer from a high density of traps and defects that can cause charge trapping and threshold voltage shift. Highly accelerated gate bias testing can be used for testing gate field effects on device reliability/stability, but care must be taken that the high acceleration biases do not invoke failure mechanisms that fall outside of normal device operation conditions. In this work, we attempt to address that aspect of high voltage gate tests in terms of threshold voltage instability and perform a comparative analysis between commercially available planar and trench SiC MOSFETs.

This study investigates hole-induced threshold voltage instability at high positive and negative gate stress in n-channel 4H-SiC power MOSFETs. Irrespective of the origin of the holes, whether it is from bandgap impact ionization in SiO 2 under high positive gate bias or from the Fowler-Nordheim tunneling under high negative bias, the threshold voltage (VT) is observed to decrease due to the accumulated fixed charge when holes fill existing oxide hole traps. Our study addresses this phenomenon of VT decrease, and the subsequent restoration of VT by the virtue of counterbalancing phenomenon such as electron-hole recombination or hole de-trapping to increase VT at positive gate bias. Therefore, threshold stability should be considered when any bias well above the recommended maximum use bias is applied.

Silicon carbide (SiC) power devices such as Schottky diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state. In this study the effects of the drift layer design of 650V SiC vertical power diodes and MOSFETs have been studied. TCAD simulations of different device designs have been performed, and fabricated device single-event burnout (SEB) properties are compared between the devices fabricated. We find that the standard 650V devices have a low area-scaled failure-in-time (FIT/cm 2 ) such that essentially no failures (0.01 FIT/cm 2 ) are expected at 400V drain-source bias (V DS ) operation and below. An improved design allows the SEB failure rate curve to be shifted downward in failure rate, such that at for a given V DS operation condition, the FIT/cm 2 can be decreased by 10 - 100 times, depending on the V DS value. This allows operation at about 75V higher V DS value with a similar SEB failure rate, allowing these devices to be used in a wider range of applications.

For high power full SiC modules, the application requires highly reliable and robust 4H-SiC diodes in parallel with SiC MOSFETs. This work introduces new large size (50A rated) 1200V and 1700V 4H-SiC diodes which exhibit excellent performance under high temperature reverse bias (HTRB) and high voltage high temperature humidity (HV -H3TRB) conditions without sacrificing critical device performance such as forward voltage dropr $\mathbf{(Vf)}$ , Schottky Barrier height and ideality factor, and reverse leakage current. In this work, we have improved the device integration scheme for diode manufacturing, which enabled the successful completion of HTRB and HV-H3TRB qualification for automotive application.

Presentation slides for the ISTFA 2023 Tutorial session “Reliability and Failure Analysis of SiC Power Devices and Modules.”

The demand is rapidly increasing for SiC MOSFETs and diodes for power electronic conversion semiconductor (PECS) applications such as electrified vehicle charging and traction, energy storage systems and industrial power supplies. These applications employ a high quantity of large-area die per system while demanding high system-level reliability under aggressive electrical and environmental operating conditions. In addition, SiC devices exhibit some failure mechanisms that are less severe than, or non-existent, in Si devices. This situation demands thorough and novel device reliability characterization and quantification. It is also driving the development of industry consortia standards and guidelines at a much faster rate, and relatively earlier in the technology maturation phase, than occurred in the Si industry. In this paper, I will review some of the key published reliability performance data, stress procedure methodologies used, and implications for key applications. I will also compare and contrast the existing guideline and standard documents and suggest directions that are being explored for future documents. I will also discuss how future guidelines and standards are being developed to cover the SiC-specific failure mechanisms for representative mission profiles for some key applications, particularly electrified vehicles.

With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

Power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state and above a VDS threshold for that device. Typically, the SEB failure rate is measured at a high blocking voltage, with the source and gate at ground potential. Here the effect of a negative gate bias, commonly applied during MOSFET switching to the blocking state, on the SEB failure rate is examined. It is observed that the SEB failure rate is only weakly dependent on the negative gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated. A negative gate bias of -8VGS in the device blocking state at 1100VDS only results in a 6% increase in the MOSFET SEB failure rate.

Wolfspeed has already reported [1, 2] the fabrication process, device characteristics, MMIC RF performance of a high-performance GaN-on-SiC HEMT featuring a 150 nm gate length (V5 process) for Ka-band applications. Excellent device performances have been demonstrated at Ka-band with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 %. In this work we present the comprehensive reliability assessment and lifetime projection of 28 V rated 150 nm gate length process technology (G28V5). Moreover, in this work Ka-band device reliability (at 31.5 GHz) has also been assessed under RF accelerated life test (RF-ALT), as well as RF high temp operating life (RF-HTOL) stress. The GaN-on-SiC HEMT wafers were fabricated and processed on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates, and the devices were assembled, at Wolfspeed in Research Triangle Park, NC, USA.

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of 4H-SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

In this work, we report the results of industrial qualification tests run on medium voltage SiC MOSFETs rated for 3.3 kV/40 A and 10 kV/15 A. The JEDEC JESD47J.01 standard was used as a guideline to conduct HTRB (High Temperature, Reverse Bias), HTGB (High Temperature, Gate Bias), and TDDB (Time Dependent Dielectric Breakdown) tests. No devices were found to have failed the qualification tests, and long oxide lifetime was projected for constant operation under positive bias. This paper also reports for the first time the results of qualification testing of the MOSFET body diode on a large population of medium voltage SiC MOSFETs. Constant current stress at a current equal to the device forward rating was applied for 1000 hours. No degradation of any device parameter was observed for 3 lots of devices at both the 3.3 kV and 10 kV voltage rating.

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

This paper discusses the reliability performance of Wolfspeed GaN/AIGaN high electron mobility transistor (HEMT) MMIC released process technologies, fabricated on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates. The intrinsic reliability performances of the 28 V and 40 V technologies, with 400 nm and 250 nm gate length, have been characterized with DC accelerated life test (DC-ALT), for which ohmic contact inter diffusion is the wear-out mechanism, and is accelerated by temperature and current. The intrinsic reliability performance of the 50 V technologies, with 400 nm gate length, have been characterized with RF-ALT, for which source-connected second field plate void coalescence is the wear-out mechanism which is accelerated by temperature. In spite of the differences in the accelerated test methodologies and wear-out mechanisms, all of the Wolfspeed GaN-on-SiC technologies demonstrate high and similar predicted lifetimes at their respective maximum recommended operating conditions. The reliability performance is supported with successful technology qualifications with zero failures, and volume manufacturing with a demonstrated low field failure rate.