The world class performance and reliability of a high-power density AlGaN/GaN high electron mobility transistor (HEMT) with an innovative sunken source connected field plate (SCFP) is reported. The optimized HEMT structure implements a novel sunken SCFP design that has significant advantages over the conventional field plated GaN HEMT. The new design reduced parasitic capacitances (Cgs and Cgd) whilst suppressing the peak electric fields in the drift region to improve breakdown voltage and reliability. This sunken SCFP demonstrates the improved RF performance and reliability with respect to leading GaN HEMT devices for x-band applications. The fabricated device produces 10 GHz performance with saturated output power >10 W/mm, linear gain >18 dB and PAE > 60% @ 50 V. The improved gain is a direct result of the reduction in Cgs and Cgd, by 15% and 60%, respectively. The increased power is achieved from lower trapping and increased drain voltage rating of 25%. Accelerated RF-driven reliability testing is shown to determine the expected lifetime of the device was >6E7 hours at 225°C junction temperature. This is a more than 2 orders of magnitude increase over the conventional field plate design.

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

This paper examines the effects of an improved source-connected field plate design used on multiple GaN HEMT gate length nodes. The modified field plate was shown to reduce the parasitic capacitances by suppressing the electric field in the drift region. As we reduced the device gate length to enable higher frequency applications, we have demonstrated the difficulty to maintain Cgd at smaller nodes. With the modified structure, we achieved a reduced Cgd > 4 fF/mm and small signal gain > 2 dB by optimizing the recessed field plate on three gate length nodes. In turn, this produced power gain improvements of 0.7 dB to 1.4 dB while maintaining equivalent power densities. As the gate length node was scaled, the rate of Cgd improvement was less effective which cause a softening of the gain improvement. This trend has demonstrated the difficulties in controlling the parasitic capacitances for GaN HEMT designs as they scale to high frequency nodes.

Wolfspeed has already reported [1, 2] the fabrication process, device characteristics, MMIC RF performance of a high-performance GaN-on-SiC HEMT featuring a 150 nm gate length (V5 process) for Ka-band applications. Excellent device performances have been demonstrated at Ka-band with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 %. In this work we present the comprehensive reliability assessment and lifetime projection of 28 V rated 150 nm gate length process technology (G28V5). Moreover, in this work Ka-band device reliability (at 31.5 GHz) has also been assessed under RF accelerated life test (RF-ALT), as well as RF high temp operating life (RF-HTOL) stress. The GaN-on-SiC HEMT wafers were fabricated and processed on 100 mm high purity semi-insulating (HPSI) 4H-SiC substrates, and the devices were assembled, at Wolfspeed in Research Triangle Park, NC, USA.

The design and performance of a 28 V, 3-stage, Ka-band, GaN-on-SiC, power amplifier MMIC with high efficiency and low gain compression are presented. At 30 GHz, the MMIC provides saturated power of 37.6 dBm with an associated PAE of 39.8%. P1dB is within 1 dB of saturated power over the 26.5-30.5 GHz band. At 30 GHz, P1dB is 37.1 dBm with an associated PAE of 37.8%. In addition, the MMIC has a low quiescent bias of 72 mA.

To enable scalable MOSFET technology in III-V semiconductor platforms, high quality semiconductor-oxide interfaces are essential. In this paper, a novel low-temperature plasma-enhanced atomic layer deposition (PEALD) technique was applied to deposit nanoscale high-k dielectrics on several III-V substrates, including InP, GaAs, InAs, and GaN. Approximately 7 nm of ZrO2 was grown and patterned to form MOSCAP structures, which were subsequently analyzed through electrical characterization to evaluate dielectric and interface quality. The oxide films fabricated were found to have interface trap densities ranging from 1010 - 1013 eV-1cm-2, and showed high capacitance densities (~ 2.5 μF/cm2). GaN and InP MOSCAPs with ZrO2 dielectric layers were found to have gate currents in line with direct tunneling phenomena and MOS mobilities approaching that of doped bulk semiconductors. Scaled InP MOSFET devices using these experimental values were also simulated using an optimized device structure.

In this paper we examined the thermal stability of ZrO2 gate dielectrics in GaN MOSFETs. The ultra-thin films were grown by low temperature plasma-enhanced atomic layer deposition (PEALD). It was determined that the high-k films required activation temperatures in excess of 400 o C. This reduced the density of interface traps below ~10 11 eV -1 cm -2 and improved the device characteristics. The 500 o C annealed ZrO2 demonstrated an increased drain current density of 5x over the nonannealed ZrO2 gate dielectric. However, annealing temperatures excess of 500 o C severely degraded the Cr/ZrO2/GaN interface and device. Likewise, Ti and Hf gate metals were unable to prevent degradation beyond 300 o C and 400 o C, respectively. The improved gate dielectric/GaN interface was achieved through the combination of a low temperature high- deposition technique followed by a post fabrication anneal.

A high effective electron mobility of 33 cm(2) V-1 s(-1) was achieved in solution-processed undoped zinc oxide (ZnO) thin films. The introduction of silicon nitride (Si3N4) as growth substrate resulted in a mobility improvement by a factor of 2.5 with respect to the commonly used silicon oxide (SiO2). The solution-processed ZnO thin films grown on Si3N4, prepared by low-pressure chemical vapor deposition, revealed bigger grain sizes, lower strain and better crystalline quality in comparison to the films grown on thermal SiO2. These results show that the nucleation and growth mechanisms of solution-processed films are substrate dependent and affect the final film structure accordingly. The substantial difference in electron mobilities suggests that, in addition to the grain morphology and crystalline structure effects, defect chemistry is a contributing factor that also depends on the particular substrate. In this respect, interface trap densities measured in high- HfO2/ZnO MOSCAPs were about ten times lower in those fabricated on Si3N4 substrates. ((c) 2014 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

The tunneling conductivity of ultrathin AlN deposited on GaN using low-temperature ALD was observed to vary significantly with n-type GaN doping concentration. While highly-doped (~10 18 cm -3 ) GaN produced consistently ohmic JV plots in a 3-6 nm AlN range, undoped (~10 14 cm -3 ) GaN only showed such a characteristic at 3 nm. Conductivity-voltage plots show that the 2DEG concentration becomes the primary influence on quantum tunneling in this case, while the transmission coefficient through AlN influences undoped GaN.

This study investigates the underlying reasons and quantifies the advantages the GaN MOSFET has over the GaN HFET for high voltage and power applications. Calibrated simulations with equivalent material model files show that equivalent dimensioned devices are capable of producing similar on-state modes of operation, and achieve similar effective mobility at equivalent larger electric fields. However, during sub-threshold operation, the GaN MOSFET is shown to contain a much lower carrier concentration than the GaN HFET. This prolongs the breakdown avalanche effect in the GaN MOSFET (3500 V) by roughly five times larger than the GaN HFET (600 V) for devices of similar dimensions. Implementing the MOS structure can potentially resolve fundamental constraints for high voltage power applications caused by current device architects.

Low-temperature (<250 degrees C) plasma-enhanced atomic layer deposition (PEALD) is used to fabricate aluminum nitride (AlN)/gallium nitride (GaN) heterojunctions for tunnelling contacts in devices where selective contacts are required, such as GaN metal-oxide semiconductor field-effect transistors. AlN is grown on GaN templates with via low-temperature plasma-enhanced ALD, and compared in order to extract their surface two-dimensional electron gas concentration. A peak electron density of >2 x 10(13) cm(-2) was observed for an approximately 4.5 nm AlN thickness on GaN wafers with a higher initial doping concentration while for the lightly doped GaN samples, a peak carrier concentration of 1.9 x 10(13) cm-2 was observed for a thickness of 5.7 nm AlN. Polarization is strongest near the AlN critical thickness of strain relaxation for low-temperature deposition methods. This suggests that greater initial dopant concentrations are more conducive to enhanced polarization characteristics under these low growth temperatures because the critical thickness is realized at lower thicknesses. This approach also yields a low contact resistance of 0.45 Omega mm with Al contacts.

ZrO2 has been deposited on GaN by Atomic Layer Deposition. Multiple Metal-Oxide-Semiconductor Capacitors with 4.4 nm, 5.4 nm, and 8.5 nm of ZrO2 oxide were fabricated with Cr electrodes. Capacitance measurements produce capacitance densities as high as 3.8 mu F/cm(2). Current densities of 0.88 A/cm(2) at 1 V for the 4.4 nm oxides and hysteresis values of less than 6 mV were observed for the 5.8 nm oxide, indicating an interfacial D-it not greater than 6.4 x 10(10) cm(2). Temperature dependent current measurements revealed no signature Poole-Frankel component. Comprehensive assessment of these measurements indicates a low defect density oxide formed on GaN with a low number of interface states. (C) 2013 AIP Publishing LLC.

A low-temperature atomic layer deposition technique for high-κ dielectric films on GaN templates was investigated for MOS applications. This improved growth method produced capacitance densities and a field effect mobility approaching 375 cm2/Vs for ZrO2 and 250 cm2/Vs for HfO2 films on GaN. Furthermore, the low density of dielectric-semiconductor interface traps confirmed a reliable cohesion between the high-κ and GaN. The improved gate dielectric deposition technique has the capabilities to improve the overall quality of GaN-based MOSFETs.

We have developed a low temperature (250 o C) plasma-enhanced atomic layer deposition process for AlN on GaN. Due to the polarization effect of the AlN/GaN interface, this growth technique has produced a large 2DEG channel (1.8x10 13 cm -2 ) and low sheet resistance (~180Ω/□). Utilizing the AlN/GaN 2DEG and ultra-thin AlN film (3 nm) we produced low ohmic contacts (~1x10 Ωcm). By simply adjusting the work function of the metal contacts we were able to modify the contact resistance of the devices. In addition, we examined the substrate leakage of low temperature PEALD fabricated GaN HFETs on various doped GaN templates.

Schottky barrier field effect transistors (SB FETs) with Schottky source injection barrier contacts are fabricated using zinc oxide (ZnO) thin films deposited by pulsed laser deposition at room temperature. In these devices, we utilize a gold Schottky barrier for the source and an aluminum ohmic metal for the drain contacts. The transistors exhibit field effect mobilities as high as 0.1 cm2 V−1 s−1, a current on/off ratio of 105, and a low saturation voltage of 6 V. When using ohmic source and drain contacts, transistor characteristics are not observed. Furthermore, the devices’ transconductance- and capacitance–voltage characteristics show a transition in the dominant carrier injection mechanism at the source barrier from thermionic emission to tunneling at a gate bias of approximately 8 V. These results demonstrate the promise of the Schottky source barrier FET architecture for building ZnO-based transistors.

ZrO2 has been deposited on GaN by atomic layer deposition. Chromium was sputtered and patterned on the ZrO2 to create Metal Oxide Semiconductor Capactors (MOSCAPs). Capacitance voltage measurements yielded capacitance density of 7.2F/cm 2 , and a mobility of 210 cm 2 /Vs. This is a fundamental step in the creation of a viable enhancement mode MOSFET.

This paper presents a capacitance model and mobility extraction method through the use of tapered transmission line theory for accumulation-mode MOSCAP test structures. The analytical model accounts for the discrepancies commonly found when measuring the capacitance of nontraditional MOSCAP architectures. Through fabrication of a planar MOSCAP, this model accurately reproduced consistent capacitance density measurements for several device dimensions and high-kappa dielectric thicknesses. In this paper, the theoretical basis of the model extracts the effective electron mobility of the accumulation channel in the semiconductor without fabricating a transistor.