Developing high performance and air-stable p-type 2D semiconductors remains a key challenge in a field that is still largely focused on n-type materials. Arsenic-phosphorus (AsP), a promising p-type candidate with improved ambient stability over black phosphorus (BP), holds strong potential for practical device applications. Despite this stability, its degradation behavior has been rarely explored from both material and device perspectives. In this study, the ambient aging behavior of AsP nanosheets is first investigated. Subsequently, multilayer AsP transistors are fabricated to systematically examine their electrical characteristics under ambient conditions. Time-resolved physical and electrical analyses over 106 h demonstrate that oxidation enhances p-type conduction while degrading noise performance. Transconductance analysis and noise modeling based on the CNF and CNF-CMF model frameworks consistently reveal changes in the dominant conduction path. This modulation of the conduction path also significantly affects the overall electrical performance and effective trap density of the device. Furthermore, an inverter circuit constructed using air-exposed AsP transistors exhibits improved switching behavior and voltage gain, confirming its potential for practical application. These findings provide fundamental insight into the ambient behavior of the underexplored AsP transistor and establish a foundation for the development of high-performance p-type semiconductors for next-generation 2D CMOS circuits.

Testing of millimeter-wave integrated circuits become increasingly challenging as operating frequencies and channel counts continue to scale, leading to high test cost and long measurement time. This paper presents an on-chip built-in self-test (BIST) architecture that enables various testing with high accuracy using internal loopback paths, compact directional couplers, and distributed power detectors. To achieve accurate power sensing within a limited area, a novel directional coupler is proposed, achieving enhanced directivity to fully separate the induced and reflected signal. The proposed BIST architecture is fabricated in a $\mathbf{2 8}-\mathbf{n m}$ CMOS technology. Measurements have been done with BIST, obtaining less than 1 dB measurement error in key RF and IF parameters. The proposed BIST architecture has acquired 82 % of internal test coverage.

This paper presents 60-and-77GHz FMCW radar RFICs with 4T/4R MIMO and cascading capability in 28nm CMOS. The RFICs demonstrate excellent RF/analog/digital performance, including > 4.8dBm TX P-SAT, 7-bit phase resolution, and > 36MHz RX IF BW, with a compact 4.5x4.5mm(2) chip size and < 2.1W power consumption. The RFICs support multiple radar modes and are validated through OTA tests, demonstrating their suitability for various radar applications.

This work presents a 60 GHz fully integrated low-intermediate frequency (IF) transceiver (TRX) for ultrashort-range (USR) frequency-modulated continuous-wave (FMCW) radars, fabricated in a 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process. The radar TRX integrates a front-end, an analog baseband (ABB), a chirp generator, and built-in self-test (BIST) circuitry that enables on-chip loopback test and self-diagnosis. It provides a wide transmitter output power dynamic range (DR) from -14 to 5 dBm to optimize the receiver signal-to-noise ratio (SNR) for various scenarios of interest. The receiver achieves an input 1 dB compression point of -6 dBm to handle strong spillover signals through a high-pass filter (HPF)-first ABB, and a noise figure (NF) of 16.6 dB at 115 kHz IF. The chirp generator based on a two-point modulation (TPM) demonstrates high linearity of 164 kHz (0.0027%) at a chirp bandwidth (BW) of 6 GHz. The proposed radar TRX has been experimentally validated for body-proximity sensing (BPS) and vital-sign monitoring (VSM) (respiration and heartbeat rates) applications. The compact design occupies a core area of 2.5 mm(2) and consumes DC power of 147 mW, making it suitable for mobile device-based solutions.

In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stage I/Q coupler. Owing to its insensitivity to I/Q mismatch and the peak error smoothing technique, the phase shifter achieves 0.33 degrees and 0.065dB rms phase and gain errors while occupying a core area of 0.17mm(2).

This paper presents 60-and-77GHz FMCW radar RFICs with 4T/4R MIMO and cascading capability in 28nm CMOS. The RFICs demonstrate excellent RF/analog/digital performance, including $>14.8 \text{dBm}$ TX $P_{\text{SAT }}$, 7-bit phase resolution, and $>36 \text{MHz}$ RX IF BW, with a compact $4.5 \times 4.5 \text{mm}^{2}$ chip size and $<2.1 \mathrm{W}$ power consumption. The RFICs support multiple radar modes and are validated through OTA tests, demonstrating their suitability for various radar applications.

A 930-GHz oscillator has been developed based on a 250-nm InP heterojunction bipolar transistor (HBT) technology. The triple-push oscillator comprises an on-chip antenna integrated with three identical unit oscillator cores, each employing a self-feeding scheme to further increase the oscillation frequency. The fabricated circuit exhibited a measured output frequency of 923.4 - 933.0 GHz, depending on the base bias voltage. Measured peak EIRP (Equivalent Isotropic Radiation Power) was -17.6 dBm, which corresponds to a radiated output power of -25.6 dBm with simulated on-chip antenna gain of 8.0 dBi. Three different test methods were compared to verify the extracted output power. The circuit dissipated a total DC power of 37.8 mW.

A 240-GHz Dicke radiometer has been developed in a 130-nm SiGe BiCMOS technology. The radiometer, based on the heterodyne configuration, employs a monolithically integrated on-chip MEMS(Micro-Electro-Mechanical Systems) switch as a Dicke switch at the front. The switch is followed by a 6-stage common-base (CB) low noise amplifier (LNA) and a single-balanced mixer driven by an external LO. The down-converted signal is amplified by an IF amplifier before sensed by an IF detector with a Gm-boosting configuration. In the paper, primary design considerations for the radiometers are first provided in terms of the key parameters, followed by the characterization results. Based on the measurement, a maximum responsivity of 325 MV/W and minimum NEP of 17.5 fW/Hz1/2 at 242.7 GHz were obtained for the circuit. The noise equivalent temperature difference (NETD) was calculated to be 1.9 K with a time constant of 100 ms.

Terahertz detectors are a key component for terahertz imaging, where detector arrays are preferred over single-pixel detectors for reduced scan time and potential for real-time imaging. While a lager pixel count is often desired for arrays, there is a limit on the maximum number of pixels that can be included in a semiconductor chip array. In this work, to overcome the pixel count limit, multi-chip technique has been applied for 600-GHz CMOS detector arrays, in which adjacent chips are stitched with wire-bonds for control and detection signal transfer. Two types of detector arrays have been developed and their electrical characteristics as well as the acquired 600-GHz test images are presented.

Understanding the interlayer charge transport in multilayer two-dimensional (2D) semiconductors is crucial for optimizing device performance and interface engineering in emerging nanoelectronic systems. In particular, the presence of significant interlayer resistance such as multilayers of ReS2 induces bias-dependent redistribution of conduction channels, resulting in channel migration vertically. Here, we experimentally investigate the contact-geometry-dependent channel migration behavior in multilayer ReS2 field-effect transistors (FETs) using a vertically stacked h-BN/ReS2/h-BN heterostructure. Devices with symmetric top contacts, symmetric edge contacts, and asymmetric (hetero) contact configurations are fabricated on the same flake. Systematic measurements of transconductance (gm), its derivative (dgm), and threshold voltage (Vth), combined with theoretical modeling based on Thomas–Fermi screening and interlayer resistor networks, reveal that top-contacted devices exhibit a downward migration of the main conduction channel with increasing drain bias. In contrast, edge-contacted devices maintain a stable bottom-centered conduction profile, independent of drain bias conditions. In the hetero-contact configuration, where the source electrode is edge-contacted, direct carrier injection into all layers enhances vertical channel selectivity, resulting in earlier onset and more pronounced channel migration even at relatively low drain bias. In addition, the field-effect mobility extracted from gₘ and its agreement with low-field mobility from the Y-function method confirms that interfacial scattering, rather than contact resistance, predominantly limits device performance. This study provides direct experimental insights into vertical charge migration in multilayer 2D materials and offers design guidelines for engineering contact strategies in future 2D FETs.

This paper presents a high-efficiency, high-gain buffer-less frequency quadrupler for E-band transceivers. To enhance harmonic generation, a T-coil is integrated into the second stage of the quadrupler, resulting in improved efficiency and conversion gain. Fabricated in 28-nm bulk CMOS process, the quadrupler achieves a peak conversion gain of 2.1 dB and a total efficiency of 5.1 % at 77 GHz with 0 dBm input power, obviating the need for additional buffer stage at E-band. The 3-dB bandwidth spans from 71 to 82 GHz, and the harmonic rejection ratio exceeds 20 dBc, while occupying a core area of 0.086 mm2.

This paper proposes a low-loss and compact switch-type phase shifter (STPS) for 5G FR2 cellular applications. The proposed structure replaces the explicit capacitors in the conventional pi-type low-pass-filter (LPF) based STPS with transistors, utilizing the parasitic capacitance of the transistors to operate as a pi-type LPF in the phase shift state and as a notch-less band-pass filter in the reference state. Consequently, it eliminates the notch characteristic in the reference state, improving phase and gain errors. A 4-bit differential phase shifter fabricated in a 28nm CMOS fully depleted silicon-on-insulator process achieves an insertion loss of 4.5-6.7 dB, an RMS gain error of 0.63-1 dB, and an RMS phase error of 2.9- 7 degrees, occupying a die area of only 0.08 mm2. The measurement results demonstrate that the proposed structure is very suitable for integration into phased array RFICs for 5G FR2 applications.

A baseband receiver (RX) with high-pass filtering and variable-gain control is presented. Spillover signal, which directly coupled from the transmitter to the receiver antenna, appears at low frequency with a large magnitude in the baseband, causing decorrelated phase noise and saturation. The 2nd-order biquad high-pass filter and 8-path notch filter effectively suppress the spillover signal. The push-pull class-AB output stage provides high linearity, and well matches to low load impedance in this work. Fabricated in a 28-nm FD-SOI CMOS process, the compact baseband RX occupies a core area of 0.309 mm2 and consumes DC power of 7.4 mW, making it suitable for low-power, ultra-short-range radar applications.

This work presents a 60 GHz fully integrated low-intermediate frequency (IF) transceiver (TRX) for ultra-short-range frequency-modulated continuous-wave (FMCW) radars, fabricated in a 28-nm FD-SOI CMOS process. This radar TRX includes a front-end, an analog baseband (ABB), a chirp generator, and loopback test circuits. It offers a wide transmitter output power dynamic range from -14 to 5 dBm to optimize the receiver SNR for various scenarios of interest. Additionally, it provides an input 1 dB compression point of -6 dBm to handle strong spillover signals through a high-pass filter-first ABB, and a noise figure of 16.6 dB at 115 kHz IF. The chirp generator based on a two-point modulation demonstrates high linearity of 164 kHz (0.0027%) at a chirp bandwidth of 6 GHz. The compact design occupies a core area of 2.5 mm(2) and consumes DC power of 147 mW, making it suitable for mobile device-based solutions.

This paper presents a 16-element 5G FR2 n260/n259 phased-array transmitter front-end integrated circuit implemented in a 28-nm CMOS fully depleted silicon on insulator device technology. A differential 3-stack configuration, an operational amplifier-based bias scheme, and a cross-tied inductor topology are employed in the power amplifier for high output power, stability, and reliability. The developed transmitter achieves out-put power of >14.2/9.4 dBm/element at an error-vector-magnitude of 5.6% (DFT-s OFDM 64QAM) with transmitter efficiency of >10/4.8%/element for n260/n259 bands.

Photo-induced doping has emerged as a promising method for doping two-dimensional (2D) material-based devices due to its simplicity and minimal damage to the channel. However, most studies have primarily focused on improving specific performance metrics such as photo-responsive properties and mobility with limited analysis on noise, which is crucial for device reliability and stability. This study comprehensively investigated both the electrical and noise characteristics of multilayer MoS₂ field-effect transistors (FETs) as a function of ultraviolet (UV) exposure time. Various performance parameters, such as field-effect mobility (μFE) and interface trap density (Dit), were extracted and compared. UV exposure induced a typical n-doping effect, with the threshold voltage shift revealing a more dominant role of oxide traps than interface traps. The 1/f noise pattern of the normalized drain current power spectral density (PSD) decreased with the UV exposure, fitting well to the CNF model in the strong accumulation region and the CNF-CMF model in the weak accumulation region. Extracted noise-related parameters indicated the filling of oxide traps near the interface by UV irradiation. These findings suggest that UV irradiation can modulate oxide traps near the interface, thereby improving the noise characteristics of MoS₂ FETs. This study provides a comprehensive understanding of the UV effects on electrical contacts, interface or oxide traps with different levels of noise.

An frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) chip operating near 140 GHz has been developed based on a 65-nm CMOS technology, subsequently packaged with a pair of silicon lenses for optimal beam alignment. The TRX consists of a wideband local oscillator (LO) chain, a high-power transmitter (TX), and a low-noise receiver (RX). The design procedures for sub-block circuits as well as integrated TX and RX are described in detail along with their measured performances. With the integrated single-chip TRX, a TX output power of 9.5 mW with a corresponding effective isotropic radiated power (EIRP) of 14 dBm was achieved along with a noise figure (NF) of 9.9 dB near 140 GHz. The chip with a size of 2930 x 830 mu m(2) consumed 350 mW of dc power. A dual-lens packaging technique has been proposed and successfully applied to the fabricated TRX chip, in which an individual dedicated lens is assigned for each of the TX and RX on-chip antennas, leading to significantly improved beam alignment as well as TX-RX isolation. A ranging experiment has been performed with the packaged radar TRX module with a chirp bandwidth of 32 GHz (128-160 GHz), which exhibited a range resolution of around 10 mm. For the chirp generation, a very short modulation period of 6.0 mu s was adopted, which would help suppress the effect of the low-frequency noise especially for CMOS-based systems.

This study develops a 600-GHz band array detector in a 65-nm CMOS technology. The unit pixel detector is based on a common-gate differential pair integrated with an on-chip differential patch antenna. A detector array was completed by arranging 36 pixels in a 6×6 configuration and integrating switches for row/column selection and signal path. The array exhibited average responsivity and NEP (noise equivalent power) of 1,320 V/W and 114 pW/Hz0.5, respectively. Imaging experiments were conducted at approximately 600 GHz by utilizing the developed array detector.

A 700 GHz integrated signal source has been developed in this work based on a 130 nm InP heterojunction bipolar transistor technology. The circuit consists of a differential 350 GHz oscillator integrated with a frequency doubler. For the oscillator, the common-base cross-coupled topology was employed, while balanced common-emitter structure was adopted for the frequency doubler. The fabricated signal source exhibited a measured output frequency around 700 GHz, with a tight frequency variation over oscillator bias current change (702.3–698.8 GHz). The circuit also showed a measured peak output power of −11.8 dBm and dc-to-RF efficiency at peak output power of 0.09%. The phase noise was measured to be −73.8 dBc/Hz at 10 MHz offset frequency. The total dc power dissipation was 74.4 mW.

This letter presents a mm-wave wideband amplifier implemented in a 130-nm SiGe BiCMOS technology operating up to 100 GHz. For the wideband operation, a new wideband technique based on low-impedance coupled line structure was proposed and adopted to the amplifier in combination with other bandwidth extension techniques. The enhancement of the amplifier bandwidth with the low-impedance coupled lines employed at the input and output matching networks is introduced in detail along with methodologies for actual implementation. The fabricated amplifier showed a peak gain of 13.2 dB with a 3-dB bandwidth of 90 GHz, covering from 10 to 100 GHz. The power consumption of the amplifier is 117 mW. The chip size is $865\times 344\,\,\mu \text{m}^{2}$ excluding probing pads.