This work reports on the development and fabrication of high electron mobility transistors with a gate length of less than 30 nm. The T-shaped gates were realized using a two-stage "bi-lithography" process that creates a T-shaped image in a bi-layer of PMMA and UVIII. This is then transferred into SiO2 gate support layer by a low damage dry-etch process. This method enables the fabrication of mechanically robust, ultra short T-gates to be realised

We report on the fabrication of 50nm metamorphic GaAsHEMTs with a very high yield and uniformity as determined by DC characterisation, and excellent RF figures of merit. The T-gates were realised using a combination of high resolution electron beam lithography using a bi-layer (rather than the usual tri-layer) of PMMA/Co-polymer and a selective wet etch to form the gate recess. With an electrical yield greater than 95 %, the devices displayed a threshold voltage of -0.445V with a standard deviation of ± 0.005V. The transconductance of the devices was 1169mS/mm 83 mS/mm and demonstrated a cut-off frequency, fT of 330GHz.

In this paper we report an array-based design methodology for the realisation of monolithic millimetre-wave integrated circuits (MMMICs). This work focuses on the realisation of a 94GHz MMMlC amplifier using an array-based approach by integrating high performance 50nm T-gate InP-HEMTs with an f, of 480GHz and a Si3N4 Metal Insulator Metal (MIM) capacitor technology formed using room temperature inductively coupled plasma chemical vapour deposition (ICP-CVD) nitride deposition together with a range of more conventional coplanar waveguide-based passive components. A single stage amplifier, predicted to have a gain of 8 dB and return loss of better than -1OdB at 94 GH& demonstrated experimentally a gain of SdB and a return loss of better than -6dB across a bandwidth of 1GHz from 89GHz to 96GHz at the designed bias point . The use of a room temperature nitride deposition process allows all passive components to he realised after active device realisation, and enables a mm-wave ??sea-of-gates?? arraybased design methodology.

A self-aligned T-gate technology for lattice-matched InP HEMTs is presented which addresses the issue of the maximization of sub 100 nm gate length device performance through the reduction of source and drain parasitic resistances. The material structure used is designed to allow the use of a non-annealed ohmic contact process, resulting from the optimization of vertical conductance through the layer stack by the introduction of an additional layer of delta doping. Use of the non-annealed process in turn allows a self-aligned process flow to be adopted reducing parasitic access resistance. In addition, carrier concentration and hence horizontal conduction through the structure is increased complementing the self-aligned process in the reduction of parasitic resistances. Self-aligned devices of 70 nm gate length were fabricated and demonstrated excellent characteristics at both DC and RF including a peak transconductance of 1500 mS/mm and an fT of 270 GHz.

In this paper, we review a range of nanofabrication techniques which enable the realization of uniform, high yield, high performance 50 nm T-gate III-V High Electron Mobility transistors (HEMTs). These technologies have been applied in the fabrication of a range of lattice matched and pseudomorphic InP HEMTs and GaAs metamorphic HEMTs with functional yields in excess of 95%, threshold voltage uniformity of 5 mV, DC transconductance of up to 1600 mS/mm and f(T) of up to 480 GHz. These technologies and device demonstrators are key to enabling a wide range of millimeter-wave imaging and sensing applications beyond 100 GHz, particularly where array-based multi-channel solutions are required.

Fifty nanometre gate length T-gates In0.52A10.48As/In0.53Ga0.47As high electron mobility transistors (HEMTs) on a InP substrate were fabricated with high resolution electron-beam (e-beam) lithography using a novel UVIII/LOR/PMMA T-gate resist stack and with a non-selective digital wet etch gate recess technology. The reproducibility of the gate lithography depends on the substrate slope when mounted on the holder of e-beam lithography tool. This mounting effect is almost eliminated by calibrating the tool using a specially fabricated marker on the wafer instead of the holder marker as in usual. Initial devices exhibited a maximum transconductance (gm) of 950 mS/mm and a current cut-off frequency (ft) of 300 GHz.

This work describes the improved uniformity of short gate length (sub100nm) T-gate lithography observed for InP HEMT devices through the development of a nonannealed ohmic contact process. The incorporation of such a process allows the reversal of ohmic and gate levels as part of a standard device process flow. This eliminates fluctuations in the gate geometry that result from the spinning of gate resists across a non-planar surface i.e. between the source and drain contacts.

An InGaAs/InAlAs based HEMT structure lattice matched to an InP substrate is presented in which drive current and transconductance has been optimized through a double-delta doping strategy. Together with an increase in channel carrier density, this allows the use of a non-annealed ohmic contact process. HEMT devices with 120nm standard and self-aligned T-gates were fabricated using the non-annealed ohmic process. At DC self-aligned and standard devices exhibited transconductances of up to 1480 and 1100 mS/mm respectively, while both demonstrated current densities in the range 800 mA/mm. At RF a cutoff frequency f(T) of 190GHz was extracted for the self-aligned device. The DC characteristics of the standard devices were then calibrated and modelled using a compound semiconductor Monte Carlo device simulator. MC simulations provide insight into transport within the channel and illustrate benefits over a single delta doped structure.

In this article, we report a procedure for the fabrication of ultrashort T gates using high resolution electron beam lithography and a PMMA/LOR/UVIII resist stack. The intermediate lift-off resist (LOR) layer improves the quality of gate lithography, and consequently, device yields. It is unaffected by wet chemical gate recessing procedures and we report the application of the procedure to the fabrication of pseudomorphic and metamorphic high electron mobility transistors (pHEMTs) with 50 nm T gates. Fabricated pHEMTs had a g(m) of 600 mS/mm, and f(t) of 200 GHz. Metamorphic HEMTs had a g(m) of 1500 mS/mm and f(t) of 350 GHz. We believe these are the fastest transistors of their kind in the world. (C) 2003 American Vacuum Society.

To address the major issues of increasing device frequency performance and reducing fabrication costs of 100 nm scale gate length III–V HEMT devices, two novel technologies developed for GaAs pHEMT are reported, namely: (i) A low resistance, non-annealed Ohmic contact technology based on a thin metallisation and highly doped In0.2GaAs/GaAs cap layer which is compatible with a self-aligned gate process. (ii) A succinic acid based gate recess etch which selectively etches the In0.2GaAs/GaAs cap required for the non-annealed ohmic contact technology, stopping on a 5-nm Al0.3GaAs etch stop layer. Incorporating both of these processes, self-aligned T-gate and nanoimprinted T-gate devices have been realised. Completed self-aligned T-gate GaAs pHEMT devices of 120 nm gate length exhibited an fT and fmax of 135 and 180 GHz, respectively, while nanoimprint 120 nm GaAs pHEMT devices demonstrated excellent DC characteristics, including a transconductance of 450 mS/mm.

An InGaAs/InAlAs based HEMT structure, lattice matched to an InP substrate, is presented in which drive current and transconductance has been optimized through a double-delta doping strategy. Together with an increase in channel carrier density, this allows the use of a non-annealed ohmic contact process. HEMT devices with 120 nm standard and self-aligned T-gates were fabricated using the non-annealed ohmic process. At DC, self-aligned and standard devices exhibited transconductances of up to 1480 and 1100 mS/mm respectively, while both demonstrated current densities in the range 800 mA/mm. At RF, a cutoff frequency f/sub T/ of 190 GHz was extracted for the self-aligned device. The DC characteristics of the standard devices were then calibrated and modelled using a compound semiconductor Monte Carlo device simulator. MC simulations provide insight into transport within the channel and illustrate benefits over a single delta doped structure.

We previously reported a procedure for the fabrication of high electron mobility transistors (HEMTs) using nanoimprint lithography [Y. Chen et al., Microelectron. Eng. 67,68, 189 (2003)] to produce T-shaped gates with 120 nm foot widths. The most recent batch of transistors fabricated by this original procedure had a peak transconductance of 450 mS/mm and fT of 40 GHz. In this article we describe a number of refinements to the original process with the main aims to improve performance and yield of devices. The work had two parallel strands. The first involved the development of improved silicon stamping tools to limit resist trenching effects and to produce stamping tools with smaller foot widths. T-shaped tools with 50 nm foot widths were produced from this work. The second strand of work was to optimize various aspects of transistor design and the imprint conditions used to fabricate gates which resulted in pHEMTs with a peak transconductance of 480 mS/mm and an fT of 75 Ghz.

We report the fabrication, DC and RF performance of 120 nm gate length GaAs pHEMT's whose T-gates were defined using electron-beam lithography and nanoimprinting. All devices were realised using novel non-annealed Ohmic contact and selective succinic acid gate recess etching technologies. The 120 nm gate length nanoimprinted devices showed DC transconductance of up to 450 mS/mm whilst e-beam defined gate devices showed f(T) and f(max) of 135 GHz and 190 GHz respectively.