In vitro cultures of native fish cell lines are of great importance, both for basic research and applied science. In particular, there is strong demand for long-term growable cell lines from breeding fish, like sturgeon. Here, we describe the culture of cells from Siberian sturgeon (Acipenser baerii) head kidney. The cells have so far been cultured over a period of 12 months (24 passages). Cytochemical and immunocytochemical examination suggests that, in vitro, the cells exhibit markers that are indicative for different cell types. In particular, fat storing cells (adipocytes) were observed, and the expression of cytokeratins and glial fibrilar acidic protein (GFAP) can be concluded on the basis of immuncytochemical analysis. The observation of different morphologies additionally underlines the heterogeneity of the cell population and matches the typical behaviour of in vitro cultures of stem/progenitor cells. Different applications can be imagined.

Adult pancreatic stem cells (PSCs) are able to differentiate spontaneously in vitro into various somatic cell types. Stem cells isolated from rat pancreas show extensive self-renewal ability and grow in highly viable long-term cultures. Additionally, these cells express typical stem cell markers such as Oct-4, nestin and SSEA-1. Although differentiation potential is slightly decreasing in long-term cultures, it is possible to keep cell lines up to passage 140. Clonal cell lines could be established from different passages and showed similar characteristics. Remarkably, one clonal cell line, generated from passage 75, showed deviant properties during further culture. Clonal cells formed aggregates, which built tissue-like structures in suspension culture. These generated 3D aggregates produced permanently new cells at the outside margin. Released cells had remarkable size, and closer examination by light microscopy analysis revealed oocyte-like morphology. A comparison of the gene expression patterns between primary cultures of passages 8 and 75, the clonal cell line and the produced oocyte-like cells (OLCs) from tissue-like structures demonstrated some differences. Expression of various germ cell markers, such as Vasa, growth differentiation marker 9 and SSEA-1, increased in the clonal cell line, and OLCs showed additionally expression of meiosis-specific markers SCP3 and DMC1. We here present a first pilot study investigating the putative germ line potential of adult PSCs.

Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.

In this paper we explore an attenuation measurement technique for PCB traces that is simple, robust, and quick enough to be a viable solution for a printed circuit board production environment. The technique is based on time domain reflectometry and transmission (TDR/T) measurements of two traces of different length. The result is the trace attenuation with respect to frequency. The technique combines well-known time and frequency domain algorithms. Comparison of experimental data to alternative time and frequency domain approaches verify the proposed technique up to 15 GHz. The importance of a low reflection signal launch design is discussed.

Special test vehicles with and without broken high frequency signal return paths were built in order to measure their impact on signal integrity. Design guidelines for the transition between different packaging levels are derived and discussed

The importance of increased accuracy in modeling and characterization of printed-circuit board wiring is highlighted through practical examples. Recommendations are given regarding model causality, bandwidth, measurement methodology improvement for both production-level and offline monitoring of impedance, roughness, and dielectric loss and their significance for system design, performance, delivery, and cost is discussed.

Transmission line models and material parameters are extracted from time and frequency domain measurements for product related low loss card and ceramic MCM test line structures up to 65GHz. All measured results are compared to results as obtained from field calculations showing the advantages and limitations of the different methods on product driven test vehicles.

Ceramic-based wiring has been used in IBM in high-performance multi-chip module (MCM) carriers since the early 1980s. These types of carriers can provide very high wiring and power densities. Conductors are generally screened on individual ceramic sheets that are laminated and sintered at greater than 900/spl deg/ C. The high temperature process requires the use of copper paste metallization with higher resistivity than bulk copper and the punched-via fabrication imposes the use of meshed ground planes. Typical MCMs can have close to 100 layers [George Katopis (1998)] with 200-400 /spl mu/m via pitch. In the case of single-chip modules (SCM), hundreds of signal I/O's on 100-200 /spl mu/rn pitch redistribute to the coarser module wiring. The fan-out, the hollow shielding, and the sparse and long vias generate large signal distortion and crosstalk between signal layers and via columns. This paper describes the modeling and measurement of representative glass-ceramic based wiring for both SCM and MCM applications.

S-parameter measurements were performed on special test lines embedded in an 8 copper metal layer test chip in order to determine the propagation constant gamma(f) and the complex characteristic impedance Z(0)(f). Measurement results will be presented for signal lines in the 7(th) metal layer showing very good agreement with FEM-simulations in the frequency range up to 20GHz.

This paper reviews sequential build-up (SBU) laminate substrate development from its beginning in 1988. It reports on developments in this technology for IBM applications since its adoption in 2000. These laminated substrates are nonuniform structures composed of three elements: a core, build-up layers, and finishing layers. Each element has evolved to meet the demands of packaging applications. Thin-film processing has greatly enhanced the wiring capability of SBU laminate substrates and has made this technology very suitable for high-performance designs. This paper focuses on the challenges encountered by IBM during the design, manufacture, and reliability testing phases of development of SBU substrates as solutions for application-specific integrated circuit (ASIC) and microprocessor packaging applications.