Following in the footsteps of the resounding success of the Ingenuity Mars Helicopter which was powered by a Qualcomm SnapdragonTM 801 system -on -chip (SoC), the Jet Propulsion Laboratory has continued its investments into high-performance spaceflight computers based on Qualcomm's Snapdragon line of SoCs. One significant achievement of these efforts is the development of the JPL Snapdragon Co -Processor (SCP), a small form -factor computer for spaceflight applications featuring the automotive-grade Snapdragon SA8155P SoC. The technology readiness level (TRL) of the SCP was raised to TRL6 in January 2024. The SCP is currently being included in two upcoming CubeSat-based on -orbit technology demonstration missions and is under consideration as a computer vision processor for missions up to and including class-B. The Snapdragon SA8155P features an octa-core Arm CPU cluster with four Cortex A-76 and four Cortex A-55 cores, a graphics processing unit (GPU) capable of 898 GFLOPs (32-bit floating-point), and a cluster of 4 HexagonTM DSP cores. The SCP board is outfitted with 16 GB of RAM, 128 GB of non-volatile Flash memory, and 2 Mb FRAM. The external interfaces of the SCP are two USB 3.1 Gen2 ports, a 4x4 lane MIPI Camera Serial Interface connector, and a 200 -pin space -grade mezzanine connector featuring three total PCI Express lanes, an RGMII interface to support Gigabit Ethernet, and low -speed UART, GPIO, JTAG, and SPI connections. To utilize the interfaces on the mezzanine connector, JPL has developed a variety of custom carrier cards for the SCP, ranging from the advanced and high-performance line of Swift Processor Modules to a dedicated SCP carrier card for CubeSat applications. In this paper, we present a detailed overview of the SCP design, its capabilities, and its interfaces to the spacecraft bus. We describe the available options to integrate the SCP into a spacecraft using the currently available and in -development carrier boards as examples. We comment on the software support and past and future JPL software benchmarking and porting efforts. Finally, we comment on the TRL-6 test campaign and give a brief outlook of the future of the SCP for JPL missions and the wider spaceflight community.

The National Aeronautics and Space Administration's (NASA) Deep Space Optical Communications (DSOC) payload, launched with the Psyche spacecraft on October 13, 2023, is facilitating an ongoing Technology Demonstration (TD) of Free-Space Optical Communications (FSOC), from beyond the earth-moon system. The DSOC Flight Laser Transceiver (FLT), can acquire a 1064 nm uplink laser from earth, and return a 1550 nm, Serially Concatenated Pulse Position Modulated (SCPPM) signal, to earth. The FLT uses a 22 cm diameter unobscured optical transceiver assembly, coupled to a 4 W average power laser transmitter, supplemented with actuators, sensors, electronics and software. A 5-7 kW average power, multi-beam 1064 nm uplink laser assembly integrated to the Optical Communications Telescope Laboratory (OCTL) near Wrightwood, CA serves as the Ground Laser Transmitter (GLT). The DSOC Ground Laser Receiver (GLR) at the Palomar Observatory, Hale telescope (operated by Caltech Optical Observatories), consists of a Superconducting Nanowire Single Photon Detector (SNSPD) array, connected to a ground signal processing assembly. Signal photon arrivals are detected and processed to extract information codewords at the GLR. A Mission Operations System (MOS) co-located with the Psyche Project Mission Operations Center, at the Jet Propulsion Laboratory (JPL), coordinates DSOC technology demonstration activities. This paper presents a system overview, mission description and operations architecture for the TD. Early results that include downlink at maximum downlink data-rate of 267 Mb/s from 0.37 Astronomical Units (AU) or 55 million kilometers are presented.

The Deep Space Optical Communication (DSOC) project will conduct its technology demonstration concurrently with NASA's Psyche mission, which hosts the DSOC flight transceiver (FLT) on its spacecraft. The DSOC Ground Laser Receiver (GLR) has been developed by the Jet Propulsion Laboratory and installed at the Palomar Observatory 5m Hale telescope in order to receive the optical downlink signal from the FLT, and is capable of processing discrete downlink data rates from 56 kbps to 265 Mbps over the course of the mission spanning an approximate range of 0.06 to 2.7 AU. In this paper we review the architecture of the completed GLR and its subsystems: (i) the GLR Optics Assembly (GLROA) that acquires the downlink signal and couples it to (ii) the GLR Detector Assembly (GDA) that features a superconducting nanowire single photon counting detector (SNSPD) array, (iii) the GLR Signal Processing Assembly (GSPA) that demodulates and decodes the pulse-position-modulated downlink waveform, and (iv) the GLR Monitor and Control software that is used to interface with the Hale telescope and operate the entire system. We discuss GLR operations in response to planned DSOC downlink activities, and present key results from end-to-end performance tests conducted with FLT hardware, as well as operational readiness test results that demonstrate Ground Laser Receiver station readiness to meet DSOC objectives.

The Deep Space Optical Communication (DSOC) project will demonstrate free-space optical communication at almost 3 AU, or 3 orders of magnitude further than any previous attempt. DSOC will utilize the 5m Palomar Hale Telescope to receive the downlink signal, which will couple the downlink light onto an optical table and into a superconducting nanowire single photon detector (SNSPD). The output of the SNSPD is digitized by the Ground Laser Receiver Signal Processing Assembly (GSPA) using a high throughput streaming time to digital converter (TDC). The GSPA is a scalable FPGA-based receiver which demodulates and decodes the DSOC downlink signal through novel signal processing algorithms implemented on Xilinx UltraScale+ FPGAs, as well as Python-based software monitor and control routines. Exploiting the unique TDC-based architecture, the GSPA supports over four orders of magnitude of downlink data rates across multiple orders of magnitude of signal and background powers. In this paper we present an overview of the hardware, firmware and software architectures to implement this system, as well as performance analysis for links ranging from near-Earth to 2.8 AU.

A low-volume low-mass low-power ultra-high-frequency radio transceiver for future planetary missions is described. The project targets a volume of less than 10 , mass of less than 50 grams, and power consumption of 50 mW on receive and 100 mW, 300 mW, or 3 W on transmit (for 10 mW, 100 mW, and 1 W output options). The transmitter design supports convolutionally coded binary phase-shift keying (BPSK), RC-BPSK, and quadrature phase-shift keying transmission from 1 to 256 kbps. Command/control instructions can be received at 2 or 8 kbps, with a sensitivity of better than 120 dBm. In addition to its low volume/mass/power features, temperature compensation to 100 C and radiation tolerance to 100 krad allow operation outside of thermally controlled, shielded enclosures, further reducing the mass and complexity of exploration vehicles. The design is described in a top-down format, beginning with system requirements and proceeding through digital modem algorithm development, discussion of the silicon-on-sapphire CMOS process used and elaboration of key blocks in the radio-frequency (RF) integrated circuit design. Techniques to address coupling between high-sensitivity RF and on-chip digital circuits are also presented, and test results are given for prototypes of all major functions. Although designed for the Martian environment, the transceiver is expected to be useful in other proximity links where a small low-power radio compatible with Prox-1 space-link protocols is desired.

A low-volume low-mass low-power ultra-high- frequency radio transceiver for future planetary missions is described. The project targets a volume of less than 10 cm3, mass of less than 50 grams, and power consumption of 50 mW on receive and 100 mW, 300 mW, or 3 W on transmit (for 10 mW, 100 mW, and 1 W output options). The transmitter design supports convolutionally coded binary phase-shift keying (BPSK), RC-BPSK, and quadrature phase-shift keying transmission from 1 to 256 kbps. Command/control instruc- tions can be received at 2 or 8 kbps, with a sensitivity of better than � 120 dBm. In addition to its low volume/mass/ power features, temperature compensation to � 100 � Ca nd radiation tolerance to 100 krad allow operation outside of thermally controlled, shielded enclosures, further reducing the mass and complexity of exploration vehicles. The design is described in a top-down format, beginning with system requirements and proceeding through digital modem algo- rithm development, discussion of the silicon-on-sapphire CMOS process used and elaboration of key blocks in the radio-frequency (RF) integrated circuit design. Techniques to address coupling between high-sensitivity RF and on-chip digital circuits are also presented, and test results are given for prototypes of all major functions. Although designed for the Martian environment, the transceiver is expected to be useful in other proximity links where a small low-power radio compatible with Prox-1 space-link protocols is desired.

A UHF half-duplex micro-transceiver for future Mars exploration missions is described. The transceiver target specifications include a volume of less than 1 cm3, mass of less than 10 grams, and power consumption of <40 mW on receive and 50 mW, 300 mW, or 3 W on transmit. It is compatible with a subset of Prox-1 protocols and supports transmission rates from 1 to 4096 ksps, depending on RF link parameters, in BPSK or QPSK format. Command and control instructions can be received at 1 or 8 ksps. In addition to its low mass/power features, temperature compensation to -100 C and radiation tolerance to 100 krad allow operation outside of large, thermally controlled, shielded enclosures, further reducing the mass and complexity of exploration vehicles. Although designed around Mars missions and environmental constraints, the transceiver is expected to be useful as well in other proximity links where a small/low-power radio compatible with Prox-1 protocols is desired

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

This chapter provides an overview of the Electra radio [1]. This is the first programmable software radio that has been developed for space missions. The radio currently accommodates digital binary phase shift keying (BPSK) modulation with both suppressedand residual-carrier capabilities. The radio is designed to operate over a wide range of data rates from 1 kilobit per second (kbps) to 4 megabits per second (Mbps) and must accommodate frequency uncertainties up to 20 kHz with navigational Doppler tracking capabilities. As such, it is highly programmable and incorporates efficient front-end digital decimation architectures to minimize power consumption requirements. The Electra radio uses field programmable gate array (FPGA) technology to provide the realtime and programmable capabilities. Emphasis in this chapter is focused on the programmable features of the software algorithms implemented in the Electra transceiver as well as the hardware functional specifications. The objective of the Electra radio, which is based on the original Micro Communications and Avionics Systems (MCAS) prototype [2], is to develop programmable telecommunications systems to meet the unique needs of the National Aeronautics and Space Administration (NASA) for low-power space and planetsurface communications. NASA is moving into an era of much smaller space exploration platforms that require low mass and power. This new era will usher in increasing numbers of miniature rovers, probes, landers, aerobots, gliders, and multiplatform instruments, all of which have short-range communications needs (in this context short-range is defined as non-deep-space links). Presently these short-range (or in situ) communications needs are being met by a combination

Abstract-A UHF half-duplex micro-transceiver measuring 1 cm3, weighing less than 10 grams, and operating at 40 mW on receive and 50mW, 300mW, or 3W on transmit is described. The micro-transceiver is being designed for future Mars exploration missions, but can be adapted for other proximity links. It supports transmission rates up to 256 ksps and higher in BPSK or QPSK format for data return and receives commandkontrol instructions at up to 8 ksps. In addition to its low masdpower features, temperature compensated circuit and system design and radiation tolerance allow operation outside of large shielded enclosures, further reducing the mass and complexity of exploration vehicles.

This article provides an overview of the communications system that is being developed as part of the Micro Communications and Avionics Systems (MCAS). The flrst phase (MCAS1) efiort is being focused on a digital binary phase-shift-key (BPSK) system with both suppressed- and residual-carrier capabilities. The system is being designed to operate over a wide range of data rates from 1 kb/s to 4 Mb/s and must accommodate frequency uncertainties up to 10 kHz with navigational Doppler tracking capabilities. As such, the design is highly programmable and incorporates e-cient front-end digital decimation architectures to minimize power consumption requirements. The MCAS1 design uses fleld programmable gate array (FPGA) technology to prototype the real-time MCAS1 communications system. Ultimately, this design will migrate to a radiation-hardened, application-speciflc integrated circuit (ASIC). Speciflc emphasis in this article is focused on the digital front end and BPSK demodulation portions of the MCAS1 receiver.

This paper provides an overview of the communications system that is being developed as part of the Micro Communications and Avionics Systems (MCAS). The first phase (MCASl) effort is being focused on a digital, binary phase shift key (BPSK) system with both suppressed and residual carrier capabilities. The system is being designed to operate over a wide range of data rates from 1 kbps to 4 Mbps and must accommodate frequency uncertainties up to 10 kHz with navigational Doppler tracking capabilities. As such, the design is highly programmable and incorporates efficient front-end digital decimation architectures to minimize power consumption requirements.’ The MCASl design uses field programmable gate array (PPGA) technology to prototype the real time MCASl communications system. Ultimately, this design will migrate to a radiation-hardened, application-specific integrated circuit (ASIC). Specific emphasis in this article is focused on the digital front end and BPSK demodulation portions of the MCAS 1 receiver.

This article provides an overview of the communications system that is being developed as part of the Micro Communications and Avionics Systems (MCAS). The flrst phase (MCAS1) efiort is being focused on a digital binary phase-shift-key (BPSK) system with both suppressed- and residual-carrier capabilities. The system is being designed to operate over a wide range of data rates from 1 kb/s to 4 Mb/s and must accommodate frequency uncertainties up to 10 kHz with navigational Doppler tracking capabilities. As such, the design is highly programmable and incorporates e‐cient front-end digital decimation architectures to minimize power consumption requirements. The MCAS1 design uses fleld programmable gate array (FPGA) technology to prototype the real-time MCAS1 communications system. Ultimately, this design will migrate to a radiation-hardened, application-speciflc integrated circuit (ASIC). Speciflc emphasis in this article is focused on the digital front end and BPSK demodulation portions of the MCAS1 receiver.

An advanced technology X- and Ka-band (8 and 32 GHz) Tiny Transmitter is being developed for the New Millennium program and is described in this paper. The Tiny Transmitter is the first development phase of the Tiny Transponder which will incorporate recent advances in miniaturization and flexibility of radio systems by utilizing digital radio techniques. These techniques incorporate digital technology and algorithms to perform many functions which have traditionally been performed by analog circuits and allow the complexity of the RF portion of the radio to be minimized. The Tiny Transponder will be able to meet the needs of many deep space missions presently being planned for launch after the year 2000

The size, mass and cost of telecommunications systems on deep space missions have increased at almost an exponential rate over the last thirty years. Great cost and size reduction of these systems can be achieved by reducing the cost and size of the transponder component of the radio subsystem. An advanced technology X- and Ka-band (8 and 32 GHz) tiny transmitter is being developed at JPL for the New Millennium program and is described in this paper. The tiny transmitter is the first phase of development of the tiny transponder which will incorporate recent advancements in miniaturization and flexibility of radio systems by utilizing digital radio techniques. These techniques incorporate digital technology and algorithms to perform many functions which have traditionally been performed by analog circuits and allow the complexity of the rf portion of the radio to be minimized. The tiny transponder will be able to meet the needs of almost all deep space missions presently being planned for launch after the year 2000.