This study explores the integration of coupling coils within Power Semiconductor Modules for sensing applications in railway traction converters. It focuses on the new high-power module devices generation called Low Voltage Module (LVM) in Roll2Rail specification [R2R16]. The research delves into coupling coil in scenarios involving short circuits and switching phases, emphasizing di/dt measurement. Integrated sensors on driver circuit demonstrate efficient short-circuit detection, and this study introduces sensor optimization through numerical simulation. Di/dt measurements through High Voltage (HV) main terminals to enable rapid detection during operational phases. A comparison of coupling coil technologies, by opposition of well-known Rogowski coils place around a conductor, highlights the possibility of using it in the region of DC minus terminals and make integration easier. This solution lowers the concerns about electrical isolation and this work highlights the potential of coupling coils in power electronics, suggesting different ways to explore for further research and development.

This paper proposes an approach to electrical and thermal modeling of a high-voltage power semicon-ductor module with a view to set up a digital twin representation for assessing degradation and remaining life of component in railway applications. Based on experimental results obtained at test bench level where optic fibers and Negative Temperature Coefficient (NTC) thermistors have been used to monitor internal temperatures of the power semiconductor module, this paper will focus on an example of fitting methodology between digital twin and real application data from tests. An application of optimization algorithm, more specifically a genetic algorithm, will be described. Results and limitation will be then discussed.

This article aims determining the minimum decoupling capacitor Cdec for a railway traction inverter. It is defined when any increase of its value does not decrease the overvoltage at turn off anymore. A simple generic model is deduced from a full understanding of the switching cell behavior, including the effect of all stray inductances and all interactions within the switching cell. This model is used in an optimization process in order to obtain directly the minimal value of Cdec. The methodology is validated in comparison with time simulation, as well as using experimental results. It has been used to analyze the impact of the switching cell parameters on the minimum value of Cdec: switching speed; stray inductances; and additional resistance have been considered.

The impact of the stray inductances originated from interconnects in power electronics becomes crucial with the next generation of SiC devices. This paper shows that the existing layout of a railway inverter, operating with Si IGBTs already exhibits a dynamic current imbalance between paralleled modules. This will not allow using this geometry with SiC MOSFETs. A complete investigation of the electromagnetic origin of this issue has been performed. A generic circuit model has been proposed to establish a cabling rule to design a Gate Distribution Printed Circuit Board (PCB) in such a way that it compensates the power dissymmetry. An optimization strategy has been used to obtain a new geometry of this PCB, which has been validated with a time domain simulation.

Chapter Contents: 7.1 Design 7.1.1 Electrical sizing 7.1.2 Size of a metallic substrate 7.2 Models 7.2.1 Modeling from a dielectric point of view: Example of optimization of electrical stress by potential distribution materials 7.2.2 Resistive material 7.2.3 Comparison between capacitive and resistive material 7.2.4 Modeling from an electromagnetic point of view: Modeling of inductances and parasitic abilities 7.2.5 Conclusion References

This paper presents a predictive short-circuit model of a SiC MOSFET chip embedded in a 3D TO package to improve simulation and prediction of short-circuit behavior at the chip level. This model describes the non-linearity and the thermoelectric behaviors of parameters such as transconductance (gm), on-state resistance (R dsON ), threshold voltage (V GSth ) and parasitic capacitances. The identification of these parameters constituting the behavioral model is based on supplier datasheets and complementary tests. This model can be used to anticipate short-circuit tests and it can be useful for the creation of a digital twin in order to refine the anticipation of reliability and understanding of solder ageing phenomena and bonding pull-out in power chips. With a 3D model and circuit approach, the variations of short-circuit currents once the component has aged can be observed during the impact of chip delamination and bonding pullout.

New High Power Half-Bridge Modules have recently been introduced in railway traction converters. They are designed to minimize stray inductance and get full benefits of modern fast switching power Si IGBT and SiC MOSFET. These new standard modules available in different voltage classes offer to the user advantage of scalability and improved power ratio. Electrical and thermo-mechanical stress distribution in the converter is also important as it can impact strongly reliability and lifetime which are key requirements for railway traction applications. Thanks to advanced multi-domain simulations based on Reduced Order Model (ROM) technique and measurements, non uniformity of current and temperature stress between chips is analyzed in case of a realistic mission profile. Electrical and thermal stress distribution is improved compared to state-of-the art converters. A very good current distribution between paralleled chips is reported (# 3 %), a reduction of temperature difference between paralleled chips (typically reduced by half) is estimated with a direct impact on lifetime.

This paper aims determining the minimum decoupling capacitor Cdec for a high speed switching cell. It is determined when any increase of its value does not decrease the overvoltage at turn off anymore. A simplified model is deduced from a full understanding of the switching cell behavior, including the effect of all stray inductances and all interactions within the switching cell. This model is used in an optimization process in order to obtain directly the minimal value of Cdec. The methodology is validated in comparison with time simulation, as well as using experimental results. It has be used to analyze the impact of the switching cell parameters on the minimum value of Cdec: switching speed, stray inductances and additional resistance are considered.

With constraints for high-level integration of electronics, new EMC behaviors have to be considered to prevent real electromagnetic compliance. Especially, in embedded and on-board device's context, environmental temperature has an influence on the circuit behavior and EMC figures. This paper deals with susceptibility studies combined with temperature effects on electronic devices used to control power and transmissions. Specific dual thermal-electromagnetic test set-up developed for this are presented. Main results of an experimental campaign on digital PCB dedicated for generation of Pulse Width Modulation (PWM) patterns are presented. Temperature dependant susceptibility and sensitivity of the PWM parameters are compared and analyzed.

A new method for analyzing the impact of materials and architectures of Power Mechatronic assemblies on the parasitic electromagnetic couplings is presented. In this paper, the stray capacitance of a single-layer iron-core solenoid is analyzed using a PEEC-based 3D method. The results are compared to an analytical calculation of turn-to-turn and turn-to-core capacitance to validate the proposed method. The solenoid is subject to an EM field calculation in order to extract the coupling coefficients between different turns and the core of the inductor. The coupling coefficient matrix is extracted and imported into a Netlist circuit formalism for further analysis and comparison with the analytical calculations. These first derived results will be helpful in the modeling works for solving EMC issues such as transient over-voltage in wound structures of power Mechatronic systems. This is a first step of The Virtual Experimentation Method for future analyzing and designing of compatible Mechatronic subsystems, by integrating materials and architecture parameters into the design process.

Ce papier presente les etudes CEM menees sur des architectures electroniques mobiles et mecatroniques. Une premiere partie presente une synthese de comportement electromagnetique a la fois sur les emissions de modules de puissance et sur l'immunite des modules de controle et commande associes. Les perspectives et etudes en cours sur les impacts CEM issus de la montee en frequence de convertisseurs, actionneurs, et du rapprochement des signaux de commande dans le systeme sont presentees.

As the integration level of power electronics equipment increases, the coupling between multi-domain physical effects becomes more and more relevant for design optimization. At the same time, virtual analysis capability acquires a critical importance and is conditioned by the achievement of an adequate compromise between accuracy and computational effort. This paper proposes the compact model development of a 6.5 kV field-stop IGBT module, for use in a circuit simulation environment. The model considers the realistic connection of IGBT and anti-parallel freewheeling diode pairs: the description of semiconductor physics is coupled with self-heating effects, both at device and module level; electro-magnetic phenomena associated with the package and layout are also taken into account. The modeling approach follows a mixed physical and behavioral description, resulting in an ideal compromise for realistic analysis of multi-chip structures. Finally, selected examples, derived from a railway traction application scenario, demonstrate the validity of the proposed solution, both for simulation of short transients and periodic operation, qualifying the model as a support tool of general validity, from system design development to reliability investigations.