In this paper, we evaluate the temperature influence on the vulnerability to single event upsets (SEU) of 6-transistor static random access memory (6T-SRAM) cells and dual interlocked storage cells (DICE). The critical charge (Q(crit), minimum charge capable of generating an SEU) is evaluated for 65nm, 45nm, 32nm and 22nm bulk CMOS technologies and temperatures between -50 degrees C and 150 degrees C. A double exponential signal is used to model the current pulse generated by ionizing particles. SPICE simulations have shown that Qcrit is sensibly reduced by the rise of temperature. Qcrit variations of up to 88.4% and 99.9% have been calculated for 6T-SRAM and DICE cells, respectively.

With the constant increase of microelectronic systems complexity and the continual scaling of transistors, reliability remains one of the main challenges. Harsh environments, with extreme conditions of high temperature and thermal cycling, alter the proper functioning of systems. For data storage devices, high temperature is considered as a main reliability threat. Therefore, it becomes essential to develop monitoring techniques to guarantee the reliability of volatile and non-volatile memories over an entire range of operating temperatures. In the frame of this thesis, I focus my studies on two types of memories: NAND Flash memories and SRAM. To monitor the effects of temperature in NAND Flash Memories, a timer-based solution is proposed in order to reduce the refresh frequency and continue to guarantee the integrity of data. For SRAM memories, the effect of temperature on Single Event Upset (SEU) sensitivity is studied. A comparative study on SEU occurrence under different temperatures is conducted for standard 6T-SRAM cells and hardened Dual Interlocked Storage Cells (DICE). Finally, statistical and computational approximation techniques based on periodic check operations are proposed in order to improve the tolerated Raw Bit Error Rate (RBER) in enterprise-class Flash based SSDs.

Solid-state drives (SSDs) based on NAND flash memories provide an attractive storage solution as they are faster and less power hungry than traditional hard-disc drives (HDDs). Aggressive storage density improvements in flash memories enabled reductions of the cost per gigabit but also caused reliability degradations. A recent large-scale study revealed that the uncorrectable bit error rates (UBER) in data center SSDs may fall far below the JEDEC standard recommendations. Here, a technique is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small SSD ratio may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. Instead of employing stronger but costly error-correcting codes a statistical approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next read operation is an indication that data needs to be refreshed. It is estimated that the tolerated RBER can be increased by more than a decade over a storage period of 3 years if the stored data are verified on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. This enables performance overhead reductions with factors between 8x and 12x as compared to systematic refresh schemes.

Increasing the number of bits per cell and technology scaling are ways to reduce the cost per gigabyte of flash memories and solid-state drives (SSDs). Unfortunately, this trend has a negative impact on data retention capability and cycling endurance. Periodic data refresh allows dealing with a reduced retention time and, indirectly, may be used to improve cycling endurance. A worst case data refresh frequency is not optimal in the presence of important temperature variations as it may become unnecessarily pessimistic and alter the SSD response latency and energy consumption. Here, a flexible data refresh methodology is proposed based on approximations of the Arrhenius-curves employed to describe the temperature impact on the retention capability of flash memories. These approximations may be implemented with the help of a small module called A-timer. For an asymmetric temperature distribution between 30°C and 70°C, it is estimated that the refresh frequency can be reduced by more than 63× and almost 3× for respectively charge detrapping and SILC failure mechanisms.