In this paper, we essentially discuss the material aspects of low temperature (≤ 600°C) polysilicon technologies. Emphasis is put on the properties of polysilicon films, depending on the way they are obtained. Solid phase crystallisation as well as pulsed laser crystallisation processes are presented in some detail, together with thin film transistor characteristics. Although not yet stabilised and despite uniformity and reproducibility problems, laser crystallisation will probably end up being the technology of choice for the manufacture of large area electronics products, because it allows the fabrication of devices exhibiting superior properties, with a reduced thermal budget.

Either at pixel or driver levels, low-temperature polysilicon (LTPS) is becoming a standard technology for the fabrication of thin-film transistors (TFTs) used in active matrix liquid crystal displays and in active matrix organic light emissive displays. Given the complexity of addressing or pixel circuits, simulation is becoming more and more necessary. In order to reach the required level of simulation efficiency, an accurate model has been developed. This model takes into account all the operating regimes, capacitors contributions, and frequency dispersion effects. In order to be able to simulate large number of matrix pixels and/or integrated drivers, this model is simple enough to allow simulator convergence. Based on 38 parameters, it presents an easy electrical parameters characterization methodology. Moreover, physical parameters use allows an easy modification of the model performances depending on polycrystalline silicon TFT technology properties and evolution.

Although it has been developed for more than a decade, low temperature polysilicon technology is far from being as mature as its amorphous silicon counterpart. This is due to much more complex processes, (e.g., laser crystallisation of the active silicon layer), that are not used at all in related industrial areas, such as the microelectronics industry. In this paper, we first present the major critical process steps of the low temperature polysilicon technology, including laser crystallisation and MOS-type oxide deposition.In a second part, we show that if high information content displays are to be fabricated with organic light emitting materials, they will certainly use a polysilicon active matrix, because of the inherent stability of this material.

The use of organic light emissive diodes (OLEDs) in flat panel displays is rapidly growing around the world. OLED-based displays are attractive, because they are lightweight, thin and compact. They do not exhibit viewing angle limitations as LCDs do. In principle they only use one glass plate (or one substrate plate), they need no back-light, no polarisers and no diffuser. Also, OLEDs need no alignment layers and there are no tilt angle requirements as in LCDs. In this paper, we present the major problems and limitations linked to the addressing of matrix-type displays using OLEDs. In particular, we show that active matrix addressing is necessary for high information content (HIC) displays and that for this particular application, polysilicon material is today the only serious candidate for thin film transistor fabrication.

If a plasma system, made of metal and grounded, is used for insulator material deposition, the environment of the plasma will be changed, i.e., the grounded wall will become isolated. Furthermore, the electrical characteristic measurement of the plasma and the bias properties will be largely affected by the wall effect. In this paper we investigate how the electrical characteristics evolve via the insulator deposition in a DECR (Distributed Electron Cyclotron Resonance) plasma system. An equivalent circuit of the wall effects is proposed and used to qualitatively explicate the observed phenomenon about the I-V measurement during the evolution. At the end of the paper, after having understood the properties of the wall effect, an experiment about a plasma anodic oxidation are successfully conducted in the insulator deposition system.

L'invention concerne les procedes de realisation de transistors CMOS et les dispositifs associes. Le procede realise des transistors d'un premier type et d'un second type en technologie CMOS dans une couche active. Le procede consiste: a graver ou rendre inactives des zones de la couche active de facon a definir (1) des ilots actifs destines a realiser les sources, les canaux de largeur determinee et les drains des transistors du premier type, respectivememt du second type, a recouvrir (2) au moins les ilots actifs par une couche isolante et a recouvrir (2) la couche isolante par une couche conductrice, a graver sequentiellement (3) l'ensemble des grilles des transistors du premier type puis l'ensemble des grilles des transistors du second type. Les dispositifs associes consistent en des dispositifs a transistors CMOS obtenus par un procede selon l'invention. Application, en particulier, a des dispositifs d'adressage et de commande d'un ecran plat a cristal liquide et matrice active.

In this work, the excimer laser induced crystallization of a-Si films on SiO2 was investigated, using a long pulse duration (200 ns) XeCl source. The microstructural analysis of the laser irradiated area, for incident energy densities comprised between the surface and full melting thresholds of the a-Si layer, respectively, was performed by scanning electron microscopy. A numerical simulation of the surface melt dynamics was also presented and compared to the experimental observations.

Comparisons of polycrystalline silicon materials are made using both density of states measurements made on thin films transistors and transmission and scanning electron microscopy micrographs. We show that in solid phase crystallised materials, in-grain defects control electrical properties whereas in laser crystallised materials, it is grain boundaries.

Polysilicon thin-film transistors (TFTs) are of great interest for their circuit application in the large area microelectronics. A successful circuit design requires an accurate prediction of the circuit performances, which in turn needs a proper modeling of the electrical device characteristics. In this present work the specific aspects of the anomalous current increase in the output characteristics, often called the “kink” effect, are analysed. A new procedure to determine the excess current is presented and we analysed the excess current for different gate voltages, temperatures and device geometries. We show that, from the parameters that can be extracted by analysing a reduced set of experimental data, the excess current can be easily predicted for any bias and temperature condition and also for devices with different geometries. These results can be used to further up-grade the modeling of the electrical characteristics of polysilicon TFTs in circuit simulators.

Polycrystalline silicon thin-film transistors (TFTs) have been fabricated by using a combined fast solid phase crystallization (SPC) process followed by excimer laser annealing (ELA). The electrical characteristics of the devices, after post-hydrogenation, show average field effect mobilities > 100 cm(2)/Vs and better noise performance, if compared to conventional SPC-polysilicon TFTs. A main advantage of the presented technique is the reduced sensitivity of the device performances to the energy density used during ELA.

A high quality SiO2 film is grown at rather low temperature by distributed electron cyclotron resonance plasma enhanced chemical vapor deposition. The influences of the O/Si atom ratio in gas phase and the deposition rate on the properties of the film are studied. The physical and chemical properties of the film are also investigated by high energy ion analysis, ellipsometry, chemical etching and infrared spectrometry. The electrical properties are evaluated by quasi-static I-U and high-low frequency C-U measurement. The characteristic curves of the SOI-MOSFET with the film are given.

Dans le contexte des écrans plats à cristal liquide, on présente dans cet article une analyse détaillée du mécanisme de cristallisation du silicium amorphe par laser à excimères.On montre en particulier que pour certaines conditions d'irradiation, les couches de silicium polycristallin obtenues permettent de fabriquer des transistors MOS présentant des mobilités n et p (respectivement de 350 et 150 cnvTVs) comparables à celles obtenues avec du matériau monocristallin sur isolant.

Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.

Modifications of noise performances induced by hot-carrier degradation in polycrystalline silicon thin-film transistors, made by excimer laser crystallization, are presented. In particular, the normalized drain current spectral density of these devices shows an evident 1/f behavior, and as the device characteristics are degraded by prolonged bias stressing, the noise performances worsen. Hot-carrier degradation results in the formation of both interface states, that have been evaluated through the analysis of the sheet conductance, as well as of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.

A systematic study of the noise performances of polycrystalline silicon (polysilicon) thin-film transistors (TFTs) made by excimer laser crystallization is presented. The drain current spectral density of these devices shows an evident 1/f behavior and the origin of the noise was attributed to carrier number fluctuations. The flat-band voltage spectral density was found to be strongly correlated with the field-effect mobility, suggesting that the microscopic mechanism causing the carrier number fluctuations involves the localized states present at the grain boundaries. The noise level in the devices with the best electrical characteristics is comparable with that observed in c-Si metal–oxide–semiconductor field effect transistors, a major improvement if compared to polysilicon TFTs made by solid-phase crystallization.

We have studied excimer laser crystallisation of a-Si films and in particular device performance as a function of the crystalline quality of the polysilicon films. For optimised irradiation conditions, we report mobilities of 350 and 150 cm2/Vs respectively for n and p-type devices and a delay time of 4 ns / stage measured at 10V on 5 ¿m CMOS ring oscillators.

Interface state creation, induced by hot hole injection, has been frequently observed in n-channel polysilicon thin-film transistors, when subjected to prolonged bias stress with negative gate biases. In this work we propose a new model for the kinetics of interface state formation, that closely links the interface state generation to the measured gate leakage current. The interface state generation mechanism appears to be driven by the recombination of hot holes (injected from the semiconductor active layer) with electrons (injected from the gate electrode). This model is shown to fit very well the time evolution of the interface states, as determined by the sheet conductance of the damaged region close to the drain.

High purity amorphous silicon layers were deposited by low pressure chemical vapour deposition (LPCVD) from either silane or disilane gases. During the solid phase crystallisation of the amorphous layers at 580 degrees C, the grain density was followed by electron microscopy and the nucleation rate at that temperature was extracted. Moreover, the variation of the grain size of the completly cristallised films as a function of annealing temperature was studied by transmission electron microscopy (TEM). The crystalline fraction was monitored by in situ electrical conductance measurements during isothermal annealings. Using these two caracterisation methods, we were able to precisely determine the thermodynamic cristallisation parameters for both types of film studied.