The possibility to realize crystalline silicon (c-Si) layers on 4H–SiC from sputter-deposited, amorphous Si within a low-temperature process is investigated by applying metal-induced crystallization (MIC). In a first experimental series, the basic performance of sputter-deposited Al, Au and Ag thin films as crystallization agents is characterized at temperatures below 275 °C. The crystallinity and orientation of the films after MIC are evaluated using X-ray diffractometry, scanning electron microscopy and transmission electron microscopy. The use of Al revealed the best orientational crystallization of Si, with a dominant <111> direction perpendicular to the interface. A strong influence of the metallic thin film microstructure on the MIC process was found. To enhance the film quality very thin Al layers were used, giving highly crystalline, epitaxially connected c-Si/4H–SiC interfaces with only few remaining Al islands.

The possibility of Schottky barrier height (SBH) modulation of conventional Ti/4H-SiC Schottky diodes by inserting an ultrathin a-SiC:H layer and the influence of annealing at 600 degrees C are investigated. Amorphous SiC:H layers between 0.7 and 4 nm thickness were grown on the 4H-SiC surface using plasma-enhanced chemical vapor deposition prior to Ti deposition. Diode properties are extracted using current-voltage and capacitance-voltage measurements between 300 and 450 K and compared to conventional Ti/4H-SiC diodes. Transmission electron microscopy and X-ray diffraction were applied to investigate the microstructure of as-deposited and annealed diodes. The integration of an a-SiC:H interface layer in combination with thermal annealing resulted in very ideal diode characteristics, whereas the duration of the annealing can be used to adjust the SBH. A room temperature SBH range between 0.78 and 1.16 V could be covered using different interface layer thicknesses and annealing durations.

Si/4H–SiC heterostructures are synthesized with low pressure chemical vapor deposition at temperatures ranging from 700 to 1080 °C. Microstructural investigations comprise scanning and transmission electron microscopy, as well as X-ray diffractometry analyses. The Si<111> and Si<110> growth orientations are found to be the most dominant, with a strong influence from the deposition temperature. Almost only Si<110> oriented and closed Si films are found at a deposition temperature of 900 °C. At the latter deposition temperature and above, the Si growth is heteroepitaxial. Heterojunction diodes by p+ and n+ doping of the Si top layer are fabricated and characterized. Strong Fermi level pinning is found to be responsible for deposition temperature dependent Schottky barrier heights.

Si/4H-SiC heterojunction diodes (HJDs) are fabricated by applying Ar + inverse sputter etching (ISE) of the 4H-SiC substrate prior to Si deposition. A subsequent annealing step was used to crystallize the sputter deposited amorphous Si. Numerical simulations and experiments were conducted to investigate the amorphization depth and etch rate of low energy Ar + ions on the Si-face of 4H-SiC. Electrical characterization of the HJDs showed a strong influence of the ISE treatment in both n and p-type Si contacts compared to untreated diodes. The ISE power, as well as the ISE time can be tailored to adjust the Schottky barrier height (SBH) in a certain range, by simultaneously improving the device ideality for most ISE parameters compared to diodes without any ISE treatment. In addition, the homogeneity of the SBHs is improved, resulting in less variation over temperature and between different samples. The formation of a smooth Si–SiC transition region instead of a sharp interface is found after both ISE treatment and thermal annealing.

The crystallization behavior of sputter-deposited amorphous silicon (a-Si) films on 4H-SiC by post-deposition annealing (PDA) is investigated. Film thicknesses between 100 and 1500 nm were selected. PDA was carried out at temperatures between 800 and 1100 degrees C. In addition, the influence of the annealing time and the heating rate is evaluated. Furthermore, the impact of high boron doping and the face of the SiC substrate was determined. A low-pressure chemical vapor deposition (LPCVD) Si film was deposited on the same substrate for reasons of comparison. The crystallinity of the Si films was investigated using X-ray diffractometry and transmission electron microscopy, whereas atomic force microscopy was applied to determine the surface roughness. The amorphous phase of the as-deposited Si thin films was crystallized into a polycrystalline microstructure applying different PDA conditions. A sharp and distinct interface to the 4H-SiC substrate without the presence of structural defects, amorphous regions or any indication for alloy formation was observed. No influence of the underlying SiC to stimulate the texture in the Si grain orientation could be found. Different PDA parameters showed an influence on the average grain size and the stress inside the grains. Highly boron-doped samples exhibit mean grain size values up to several hundreds of nanometers. Although starting with a poor film quality represented by an amorphous microstructure due to sputter deposition at low substrate temperatures, polycrystalline Si layers on 4H-SiC substrates are realized exhibiting a more than twenty times lower surface roughness compared to those synthesized with LPCVD.

In this work, the impact of the AlN/Pt ratio on the strain-sensitive properties of multilayered AlN/Pt thin films is investigated. These thin film systems consisting of 10 bi-layers of AlN and Pt each with a thickness of 3 nm AlN and 7 nm Pt or 5 nm AlN and 5 nm Pt are fabricated, evaluated and compared to those realized with a sequence of 7 nm AlN and 3 nm Pt thin bi-layers. The thin film systems are sputter-deposited on oxidized silicon wafers or sapphire substrates. The influence of different annealing steps at 900 degrees C up to 24 h in Argon (Ar) atmosphere on the electrical film resistivity and the temperature coefficient of the electrical resistance (TCR) is investigated for these different multilayers using Van-der-Pauw measurements up to 330 degrees C in air. Furthermore, the impact of the AlN/Pt-ratio on the gauge factor of the thermally stabilized multilayers is determined using a purpose-built measurement setup up to 500 degrees C in air. Transmission electron microscopy and X-ray diffraction analyses are utilized to examine the microstructure and the crystallographic phase composition of the multilayers before and after thermal loading. Annealing the different multilayers at 900 degrees C leads to diffusion effects between the AlN and Pt thin films and recrystallizations processes in the Pt sublayers depending on the individual sublayer thickness values. After thermal pre-conditioning at 900 degrees C for 1 h in Ar the samples were stable even in air up to 500 degrees C. Finally, it is shown that the TCR as well as the gauge factor of an AlN/Pt multilayer can be tuned through the AlN/Pt-ratio. The highest gauge factor with a value of 4.7 (+/- 0.3) at room temperature is achieved with a multilayer consisting of 5 nm AlN and 5 nm Pt (pure Pt thin film on Cr adhesion promotor: 3.2), while the lowest linear TCR with a value of alpha = 7.4.10(-4) K-1 is measured for multilayers with 7 nm AlN and 3 nm Pt sublayers (pure Pt thin film on Cr adhesion promotor: 3.66.10(-3) K-1). (C) 2020 Elsevier B.V. All rights reserved.

Metal induced crystallization using aluminum (Al) as catalytic metal was applied to achieve low-temperature crystallization of amorphous silicon (a-Si) on 4H-SiC. Epitaxial crystallization of Si grains was found to occur on off-axis 4H-SiC at very low temperatures using X-ray diffractometry (XRD). In-situ heating XRD measurements revealed an onset of the crystallization process at temperatures as low as 220 °C on Si- and C-face SiC, respectively. Cross-sectional imaging with scanning electron microscopy showed an almost complete layer transfer between Si and the Al metallization after annealing.

In this paper, we investigate the impact of plasma power and plasma exposure time on the Schottky barrier height (SBH) and the ideality factor of silicon carbide (SiC) Schottky diodes. N-doped 4H-SiC Schottky diodes with molybdenum nitride (MoN) top metallization are fabricated. The plasma power P-ISE is varied from 0 up to 300 W at a constant plasma time of 300 s. High resolution transmission electron microscopy is performed showing a similar to 6 nm thin amorphous layer formed at the MoN/4H-SiC interfaces after ion bombardment. Current Voltage-Temperature measurements are conducted in a wide temperature range from 50 K up to 500 K. SBHs are extracted using standard techniques, showing a significant influence of PISE on the SBH. A SBH of about 1 V is measured for diodes without ion pretreatment (P-ISE = 0 W). The highest SBH of 1.1 V is extracted for the diode with P-ISE = 50 W, followed by a continuous decrease of the SBH at higher plasma powers. At a P-ISE = 300 W, a SBH of 1.02 V is obtained, which is close to the SBH at P-ISE = 0 W. These results show that, ion bombardment increases the SBH. However, similar SBHs can be obtained by optimizing the plasma power when ion bombardment is required. Additionally, the plasma time is varied from 0 s up to 420 s by simultaneously holding the plasma power constant at 300 W. The activation energy of the investigated Schottky diodes is extracted from Arrhenius plots obtained at different voltages from-1 to-5 V. These results are in good agreement SBH evaluation. The influence of ion bombardment on SBH homogeneity on wafer level is presented. It is shown that the standard deviation of SBH on 4-inch wafers can be reduced by a factor of 2.7 when ion bombardment is used, compared to diodes fabricated without ion bombardment.

p-Si/4H-SiC heterojunction diodes are realized by sputter-deposition of the Si top contact and subsequent post-deposition annealing at either 900 degrees C or 1000 degrees C. The high Schottky barrier height (SBH) of this junction architecture of around 1.65 V is ideal to analyze SBH inhomogeneities present in most Schottky- and heterojunctions. Current-voltage-temperature (IVT) and capacitance-voltage-temperature (CVT) measurements are conducted in a wide temperature range from 60 K up to 460 K while applying standard techniques for SBH extraction. Strong deviations from ideal IV characteristics are present especially at lowest temperatures when assuming a homogenous SBH. Additionally, the extracted SBHs at low temperatures differ a lot between the two methods, indicating the presence of low barrier conduction paths. The presence of at least two distinct SBH inhomogeneities is found, which are labeled as 'intrinsic' and 'extrinsic'. Next, the Tung model was applied to fit the measured IVT data using a discretized Gaussian distribution of patch parameters to account for spreading resistance effects. By using multiple Gaussian distributions, excellent fitting results were achieved, giving the density values of the different patches and a background barrier height from the IVT data, which are in excellent agreement with the CVT data over a wide temperature range of 400 K.

In this study, the electro-mechanical properties of multilayered thin films consisting of 10 bi-layers of 7 nm aluminum nitride (AlN) and 3 nm platinum (Pt) are investigated in the as deposited state and after different post deposition annealing steps. The multilayers are deposited using direct current magnetron sputtering on thermally oxidized silicon wafers or sapphire substrates and are annealed in Ar atmosphere at 800, 900 and 1000 degrees C up to 24 h. The electro-mechanical properties are characterized from room temperature up to 500 degrees C using Van-der-Pauw as well as gauge factor measurements. Furthermore, transmission electron microscopy and energy dispersive X-ray analyses are used to investigate the microstructure and the chemical composition of the multilayers before and after thermal loading. The influence of the annealing on the crystalline structure is examined by X-ray diffraction analyses. Annealing in this high temperature range causes an intermixture of the individual Pt and AlN sub-layers as well as a recrystallization of the Pt thin films. Annealing the multilayered thin film system at 900 degrees C for 1 h in Argon atmosphere results in a multilayer which is electrically stable up to 500 degrees C in air and which exhibits a 3 times lower temperature coefficient of resistance at a similar gauge factor when compared to pure Pt thin films. (C) 2019 Elsevier B.V. All rights reserved.

In this study the influence of film thickness, adhesion promoters such as chromium (Cr) and rutile titanium dioxide (TiO2), sputtering power and substrate temperature on the electro-mechanical properties of platinum (Pt) thin films is investigated. The bilayered samples consisting of an adhesion promoter and a Pt thin film are deposited using direct current magnetron sputtering on sapphire substrates and characterized by Van-der-Pauw as well as gauge factor measurements up to 500 degrees C in air. Additionally, transmission electron microscopy and energy dispersive X-ray spectroscopy analysis are performed to investigate the microstructure and the chemical composition of the thin films before and after temperature loading. No substantial impact of the Pt film thickness on the electro-mechanical properties is determined. The diffusion of Cr into the Pt thin film at elevated temperatures leads to a lower gauge factor with a higher scatter range. Furthermore, higher sputtering power and substrate heating during deposition lead to a higher crystallinity of the Pt thin film and thus promote higher gauge factors. (C) 2018 Elsevier B.V. All rights reserved.

In this paper, four widely used interface trap characterization methods based on quasistatic and high-frequency capacitance–voltage (CV) and conductance–frequency (Gω) measurements are evaluated at thermally oxidized 4H-SiC metal oxide semiconductor structures. To cover a wide range of defect levels in a wide bandgap semiconductor, the CV and Gω measurements are conducted at temperatures ranging from 150 to 600 K. Interface trap densities Dit are extracted using the high-frequency Terman method, the low frequency capacitance method, the high-low frequency method, and the conductance method. A very good agreement between the different methods is observed in restricted energy ranges. The use of the conductance method allowed for the determination of defect states in an energy range of almost 800 meV. A strong hysteresis of bidirectional CV curves is observed at different temperatures and is used to estimate border trap densities. The presence of mobile charges in the oxide is found to be a limiting factor for high temperature CV measurements. Low temperature Gω measurements revealed a second conductance peak which is identified as the 100 meV nitrogen donor level.