This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO 2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [ 1 , 2 , 4 , 5 ]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [ 1 – 3 , 5 , 6 ]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [ 1 , 3 , 4 , 9 ]. The transient behavior of the inverter circuit is evaluated using 180[Formula: see text]nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations.

This paper presents a comprehensive analysis of power dissipation and propagation delay in 2-bit SRAM configurations ranging from 7T to 10T, building upon previous work on 6T 2-bit/4-state SWSFET SRAM designs. The study compares the performance of SWSFET SRAMs with CMOS-based 2-state SRAMs [7], highlighting the former’s significant advantages in speed and power consumption. Utilizing Cadence simulations and models such as Analog Behavioral Model (ABM) and EKV (Enz–Krummenacher–Vittoz), the analysis incorporates real-world 0.18-[Formula: see text]m technology considerations. The research explores the design nuances of 7T–10T SRAM configurations using SWS-FETs, leveraging their unique characteristics like vertically stacked quantum well/quantum dot channels. Power dissipation analysis reveals varying trends across different SRAM configurations, with notable shifts in voltage changes during transitions. Similarly, propagation delay assessments showcase diverse durations for different voltage transitions, underscoring the impact of SRAM configuration changes on efficiency and complexity. In addition, parasitic capacitance is crucial for optimizing the performance, power efficiency, and reliability of SRAM cells. In these circuits an internal storage parasitic capacitance of 1[Formula: see text]fF has been considered to evaluate its effects through simulation-based analysis during the memory cell design process. The findings contribute valuable insights into the trade-offs involved in SRAM design, particularly concerning power dissipation and propagation delay, and are presented. Overall, this study sheds light on the promising potential of SWS-FETs for enhancing memory circuitry performance.

Static random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM. Ternary, quaternary, and higher-order logic (MLV) systems have shown the potential in overcoming these limitations in increasing the information density compared to the traditional binary system. The quantum dot channel field-effect transistor (QDC-FET) and quantum well Spatial Wavefunction Switched field-effect transistor (SWS-FET) are a new alternative with multiple operating states, low power consumption, and smaller footprints. This work presents a new four-state SRAM design that uses SWS-FET and compares it with Voltage-Mode CMOS Quaternary logic design. In addition, this work studies the noise margin in the memory circuit of the quadrilateral logic system and its effect on data stability. Furthermore, this study shows the reliability of quaternary SRAM design by evaluating the impact of errors.

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices.

This paper presents the experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO2 and Ge/GeO2 quantum dots. The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge quantum dot layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow the reduction of FET count in logic block in microprocessors.

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) [Formula: see text]-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.

This paper presents quantum dot channel (QDC) FETs in quantum wire and coupled quantum dot configurations for cryogenic operation with multi-state operation. It also describes gate-all-around (GAA) quantum dot channel (QDC) FETs that exhibit potential multi-state characteristics at room temperature. FETs with cladded Si and Ge quantum dot layers as a transport channel have been fabricated. The formation of a quantum dot superlattice (QDSL) when SiOx-cladded Si and/or GeOx-cladded Ge quantum dots (QD) are assembled results in mini-energy sub-bands in the conduction and valence band. The intra-mini-energy band transitions results in significant changes in the drain current when gate and/or drain voltages are varied. This novel feature provides a pathway for 16-/32-state logic in CMOS-X configuration. The gate-defined Si quantum dot FETs, comprising of tunnel barrier coupled, have been reported for quantum computing at cryogenic temperatures.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

This paper presents preliminary results of a high speed 1550 nm indium gallium arsenide (InGaAs)-based mesa-type modified uni-traveling carrier photodiode (M-UTC-PD) structure. Conventional UTC-PD refers to P-I-N type photodiodes which selectively use electrons as active carriers. Photons absorbed in the relatively thin P-type absorber create minority carriers which are field accelerated toward a depleted collector thereby establishing high velocity ballistic transport, making these structures applicable for high speed applications. The M-UTC-PD structure presented uses spatially tailored P-type absorber regions to limit minority carrier generation both in the lateral and axial dimensions. Utilizing an otherwise conventional UTC-PD epitaxial structure where the top P-type layers are undoped, the spatially tailored P-type regions are defined by closed ampoule Zinc diffusion techniques. The M-UTC-PD structure presented utilizes a series of nested p-doped rings within a mesa structure to limit dark current and reduce overall capacitance to improve high speed operation. Two photodiode structures will be investigated for this research project, a conventional UTC-PD structure and a modified structure, utilizing similar device designs, epitaxial designs and fabrication processes. The conventional structure will be utilized for fabrication process development, verification of epi quality and development of rapid prototyping approach toward chip-based testing and subsequent high speed RF testing procedures. Conventional UTC-PD device results will be used as a comparison to quantify the performance of the M-UTC-PD structure utilizing Zn-doped defined p-type absorber regions. Results are given for chip tests of UTC-PD chips verifying epitaxial quality and fabrication process, subsequent testing of packaged devices and RF analysis remains. Process development of the Zn-doped devices is underway, once completed, these devices will be compared to the base design to quantify performance enhancement associated with the modified design.

A novel gain and index tailored (GIT) external cavity laser (ECL) is presented. The single frequency laser demonstrates high power operation in excess of 250 mW and shot noise limited relative intensity noise (RIN) at 100 mW. This laser source is an ideal source for intensity-modulated direct detection (IMDD) photonic links. Link budget analysis is completed based on measured RIN and optical power. The analysis demonstrates that there are significant radio frequency performance advantages to operating at higher optical power while maintaining low RIN.

This paper presents fabrication of multi-state inverters incorporating SiO x -cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.

A novel magnetostrictive thin film fiber sensor is presented which can be utilized in an interferometric architecture. The magnetostrictive fiber sensor utilizes novel fiber and thin film technology to achieve high sensitivity in the sub-nanotesla regime. The base sensor architecture utilizes optical fiber wound in a novel low stress flat coil resembling a record, coated with a thin magnetostrictive film. Two prototype variants were fabricated, incorporating FeCo sputtered films of different thicknesses on 4 μm polyimide jacket single mode fiber. The sensors were incorporated into a fiber optic interferometric measurement apparatus to characterize time-varying magnetic field sensitivity. Device results are presented which demonstrate sensitivity is a function of film thickness. The experimental data exhibited a two-order magnitude sensitivity improvement as the thin film thickness was doubled. Sensitivity projections are made based on film thickness.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.