This work introduces an innovative flip-flop circuit utilizing multi-state quantum dot gate FETs, quantum dot gate and quantum dot channel FETs, and quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FETs). The SWS-FET features two or more vertically stacked quantum-well or quantum dot (QD) layers, where the gate voltage controls carrier localization within each channel. By leveraging spatial positioning to encode multiple logic states and facilitating carrier transport through mini-energy bands in a GeOx-Ge/SiOx-Si quantum dot superlattice (QDSL), the design achieves 8-state operation. Built upon the 8-state inverter using QDC SWS-FETs in a CMOS-X configuration, this approach introduces a novel paradigm for developing advanced registers and sequential circuits. The proposed design enhances performance by minimizing the silicon footprint.

This paper describes a quantum dot (QD) quantum interference transistor (QUIT) having two identical electron transport channels with variable gate or stub voltages to control [Formula: see text]–[Formula: see text] characteristics. The two channels share common [Formula: see text]–[Formula: see text] source ([Formula: see text] and drain ([Formula: see text] contacts. The [Formula: see text] region of [Formula: see text] in both arms is separated by a thin barrier layer (e.g. SiO 2 , HfO[Formula: see text] from the [Formula: see text] SiO[Formula: see text] cladded Si coupled quantum dots. Here, eight-to-twelve QDs form a finite quantum dot superlattice (QDSL) exhibiting sharp mini-energy bands. The switching in QD-QUIT is controlled by: (i) difference in tunneling barrier gate voltages VGTB in both arms at a given VDS, (ii) gate voltages on QD clusters in each arm, (iii) axial current or magnetic field along [Formula: see text]-axis perpendicular to the [Formula: see text]–[Formula: see text] plane via Aharonov–Bohm effect. The finite QDSL electron transport channel is proposed for spin-based qubits operating at cryogenic temperatures. Furthermore, the finite QDSL, constructed using doped 29Si isotope is known to improve coherence time while using more than two electrons. In particular, we present eight-coupled QDs forming a finite quantum dot superlattice (F-QDSL) exhibiting sharp mini-energy levels with very high microwave/millimeter wave/IR operations. Novel multi-state QDC [Formula: see text]-FETs realized on [Formula: see text]-epi along with [Formula: see text]-QDC-FETs are reported in a CMOS-like logic. In addition, application of quantum dot channels (QDC) [Formula: see text]-FETs and [Formula: see text]-FETs is discussed to change states of QD-NVRAMs for in-memory computing. Finally, cryogenic QD-QUITs, [Formula: see text]- and [Formula: see text]-FETs, multi-electron Si coupled quantum dots are investigated to form exchange only (EO) grids for quantum computing.

Contemporary research has identified a variety of vulnerabilities and exploits targeting automobiles that exploit the controller area network (CAN) bus. Furthermore, physical unclonable functions (PUF) can be used to fingerprint devices and generate unique secret keys. The use of common hardware such as SRAM can enable PUFs to be developed even on lowend devices. We propose a Controller Area Network Message Authenticating Intrusion Detection system (CAN-MAID) as a security protocol capable of being retrofitted onto preexisting vehicles. CAN-MAID can be used to detect illegitimate messages sent on the CAN bus and be supplemented with other modern countermeasures to improve security according to the computational capabilities of in-car computers.

In this paper, we present the design, fabrication and performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) utilizing magnesium (Mg) metal as the metal interconnect layer. We review the material properties of magnesium that enable its use in transient electronics, discuss fabrication techniques for integrating magnesium into semiconductor platforms, and evaluate the degradation mechanisms under various environmental conditions. Furthermore, basic logic gates are fabricated and tested using magnesium-based MOSFET devices. Magnesium in water degrades, forming magnesium hydroxide and releasing hydrogen, [Formula: see text]. By addressing the challenges of scalability, stability, and degradation control, this work aims to contribute to the broader adoption of degradable electronics. The integration of magnesium interconnects not only aligns with the principles of green technology but also opens new avenues for innovation in fields such as bioelectronics and environmental monitoring.

This study presents the design, simulation, and validation of a quaternary NAND logic gate based on Spatial Wavefunction Switched Field-Effect Transistors (SWS-FETs) integrated with pMOS transistors and pseudo-logic techniques. This design capitalizes on the advantages of Multi-Valued Logic (MVL), offering lower power consumption and reduced circuit complexity. The simulation, performed using Cadence OrCAD 180[Formula: see text]nm technology, validates the effective performance of the proposed logic gate across four discrete voltage levels. The study further demonstrates the implementation of both quaternary inverters and quaternary AND gates by leveraging the proposed SWS-based quaternary NAND configuration. These logic gates were designed by cascading the NAND gates in specific arrangements, validating the versatility and logical completeness of the approach. The successful realization of these components marks a key step toward developing scalable, energy-efficient MVL systems.

This paper investigates the effect of lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator on the propagation delay of a 4-state quantum spatial wavefunction-switched (SWS)-CMOS-based inverters and SRAMs. The novelty is the smaller density of interface states which reduces the fluctuations in the various threshold voltages of the SWS-FETs and logic and memory devices using them. Two SWS-CMOS-based inverter models using SiO 2 and lattice-matched II–VI ZnS-ZnMgS stack as the gate insulator, are presented. Cadence simulations are used for comparing the single stage propagation delay of each inverter and their four-state logic transitions.

This paper aims to assess the power dissipation of a threshold quantizer (TIQ) 2-bit-based comparator using a SWS-FET-based inverter [ 1 , 2 , 4 , 5 ]. Unlike conventional comparators, SWS-based comparator functionalized with TIQ comprises two or more vertically stacked quantum dots or well channels [ 1 – 3 , 5 , 6 ]. Herein, power dissipation analysis of the simulated circuit is carried out using Cadence by integrating the Berkeley Short-Channel IGFET Model (BSIM) and the analog behavioral model (ABM) [ 1 , 3 , 4 , 9 ]. The transient behavior of the inverter circuit is evaluated using 180[Formula: see text]nm technology node. Our results demonstrated a significant reduction in power dissipation which overcome the limitation of previous 4-state logic implementations.

This paper presents in-memory computing using fast write/erase quantum dot (QD) nonvolatile random access memory (NVRAM). In comparison to NVMs, multi-state NVRAMs offer enhanced Compute-In-Memory capability for applications in deep neural network architecture. Dot product is the methodology that enables an array structure for multiply and accumulate (MAC) operation. We show an approach to dot product computation using multi-state quantum dot channel (QDC) FETs and QD-NVRAM.

This paper describes fabrication of Quantum Dot Gate n-FETs using SiOx-cladded Si quantum dot self-assembled on the tunnel gate oxide. Experimental I-V characteristics exhibiting 4-states are presented. Simulation is presented for the operation of viable 4-state SRAMs using QDG-FETs.

This paper describes the fabrication of quantum dot gate (QDG) [Formula: see text]-FETs using GeOx-cladded Ge quantum dot self-assembled on tunnel gate oxide. Experimental I–V characteristics exhibiting 4-states are presented. Simulations are presented for the operation of a viable 8-state SRAM using QDG-FETs.

This paper presents quantum dot channel (QDC) FETs in quantum wire and coupled quantum dot configurations for cryogenic operation with multi-state operation. It also describes gate-all-around (GAA) quantum dot channel (QDC) FETs that exhibit potential multi-state characteristics at room temperature. FETs with cladded Si and Ge quantum dot layers as a transport channel have been fabricated. The formation of a quantum dot superlattice (QDSL) when SiOx-cladded Si and/or GeOx-cladded Ge quantum dots (QD) are assembled results in mini-energy sub-bands in the conduction and valence band. The intra-mini-energy band transitions results in significant changes in the drain current when gate and/or drain voltages are varied. This novel feature provides a pathway for 16-/32-state logic in CMOS-X configuration. The gate-defined Si quantum dot FETs, comprising of tunnel barrier coupled, have been reported for quantum computing at cryogenic temperatures.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.

This paper presents a novel D-latch circuit using multi-state quantum dot channel (QDC) spatial wavefunction-switched (SWS) field-effect transistors (FET). The SWS-FET has two or more vertically stacked quantum-well or quantum dot (QD) layers where the magnitude of the gate voltage determines the location of carriers in each channel. Spatial location is used to encode multiple logic states along with the carrier transport in mini-energy bands formed in GeOx-Ge/ SiOx-Si quantum dot superlattice (QDSL), and to obtain 8-states operation. The design is based on the 8-state inverter using QDC SWS-FETs in CMOS-X configuration. This could be a new paradigm for designing flip-flops and registering more complex sequential circuits. The proposed design leads to reduced propagation delay and a smaller Si footprint.

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.

Designing secure architectures for IT infrastructure is a difficult process that needs mechanisms to provide security risk metrics that can help guide the system design process. It is through this evaluation process that a designer can ensure that implementations of a model meet the necessary security-based requirements. This work presents a scheme called TAMSAT for translating early-stage system architecture design models into security-based attack trees, which are evaluated for security risk. These attack trees can be evaluated around a set of assets of importance, whose security risk is classified by a monetary value. This security risk value can inform the system designer and provide input into an iterative design process, as well as illuminate unexpected sources of potential future security issues.

Embedded systems are designed to have security measures in place that protect users' data from software and network attacks, but these measures can prove useless when the attacker gains physical access to the system. Research has shown that dynamic random access memory (DRAM) is vulnerable to attacks that take advantage of its remanence property where data remains in DRAM shortly after the system is powered off. In this paper, we propose a method utilizing both cache locking and encryption to secure the DRAM on any embedded system by modifying the cache architecture of the CPU. We demonstrate an implementation using a MicroBlaze CPU, but the design can be used with any FPGA soft-core CPU, even if it does not have pre-existing cache locking capabilities. The cache modifications introduce almost no impact on performance and minimal extra hardware utilization.

Physical Unclonable Functions (PUFs) are probabilistic circuit primitives that extract randomness from the physical characteristics of a device. PUFs are easy and simple to implement and its random nature makes its behavior hard to predict and model. Most existing PUF designs are based on variation at the chip level and can not be implemented in a printed circuit board (PCB). Therefore, these PUFs can not be used to protect against counterfeit PCBs in a distributed supply chain. In this work, we propose a novel PUF design based on resistor and capacitor variations for low pass filters (LoPUF). We demonstrate the setup in a protoboard for different resistor-capacitor pairs (RC pairs) for reliable low pass filter PUF. Because of process variations, the voltage will be different at the same cut-off frequency for our proposed PUF. Finally, the output of the filter is connected to an inverter to measure the pulse width and best suitable pulses are used for ID generation based on our algorithm.