Programming applications on heterogeneous systems with hardware accelerators is challenging due to the disjoint address spaces between the host (CPU) and the device (GPU). The limited device memory further exacerbates the challenges as most data-intensive applications will not fit in the limited device memory. CUDA Unified Memory (UM) was introduced to mitigate such challenges. UM improves GPU programmability by supporting oversubscription, on-demand paging, and migration. However, when the working set of an application exceeds the device memory capacity, the resulting data movement can cause significant performance losses. We propose a tiling-based task-parallel framework, named DeepSparseGPU, to accelerate sparse eigensolvers on GPUs by minimizing data movement between the host and device. To this end, we tile all operations in a sparse solver and express the entire computation as a directed acyclic graph (DAG). We design and develop a memory manager (MM) to execute larger inputs that do not fit into GPU memory. MM keeps track of the data on CPU and GPU, and automatically moves data between them as needed. We use OpenMP target offload in our implementation to achieve portability beyond NVIDIA hardware. Performance evaluations show that DeepSparseGPU transfers 1.39x-2.18x less host to device (H2D) and device to host (D2H) data, while executing up to 2.93x faster than the UM-based baseline version.

Recently, several task-parallel programming models have emerged to address the high synchronization and load imbalance issues as well as data movement overheads in modern shared memory architectures. OpenMP, the most commonly used shared memory parallel programming model, has added task execution support with dataflow dependencies. HPX and Regent are two more recent runtime systems that also support the dataflow execution model and extend it to distributed memory environments. We focus on parallelization of sparse matrix computations on shared memory architectures. We evaluate the OpenMP, HPX and Regent runtime systems in terms of performance and ease of implementation, and compare them against the traditional BSP model for two popular eigensolvers, Lanczos and LOBPCG. We give a general outline in regards to achieving parallelism using these runtime systems, and present a heuristic for tuning their performance to balance tasking overheads with the degree of parallelism that can be exposed. We then demonstrate their merits on two architectures, Intel Broadwell (a multicore processor) and AMD EPYC (a modern manycore processor). We observe that these frameworks achieve up to 13.7 × fewer cache misses over an efficient BSP implementation across L1, L2 and L3 cache layers. They also obtain up to 9.9 × improvement in execution time over the same BSP implementation.

Achieving high performance and performance portability for large-scale scientific applications is a major challenge on heterogeneous computing systems such as many-core CPUs and accelerators like GPUs. In this work, we implement a widely used block eigensolver, Locally Optimal Block Preconditioned Conjugate Gradient (LOBPCG), using two popular directive based programming models (OpenMP and OpenACC) for GPU-accelerated systems. Our work differs from existing work in that it adopts a holistic approach that optimizes the full solver performance rather than narrowing the problem into small kernels (e.g., SpMM, SpMV). Our LOPBCG GPU implementation achieves a 2.8 × –4.3 × speedup over an optimized CPU implementation when tested with four different input matrices. The evaluated configuration compared one Skylake CPU to one Skylake CPU and one NVIDIA V100 GPU. Our OpenMP and OpenACC LOBPCG GPU implementations gave nearly identical performance. We also consider how to create an efficient LOBPCG solver that can solve problems larger than GPU memory capacity. To this end, we create microbenchmarks representing the two dominant kernels (inner product and SpMM kernel) in LOBPCG and then evaluate performance when using two different programming approaches: tiling the kernels, and using Unified Memory with the original kernels. Our tiled SpMM implementation achieves a 2.9 × and 48.2 × speedup over the Unified Memory implementation on supercomputers with PCIe Gen3 and NVLink 2.0 CPU to GPU interconnects, respectively.

Data movement is an important bottleneck against efficiency and energy consumption in large-scale sparse matrix computations that are commonly used in linear solvers, eigensolvers and graph analytics. We introduce a novel task-parallel sparse solver framework, named DeepSparse, which adopts a fully integrated task-parallel approach. DeepSparse framework differs from existing work in that it adopts a holistic approach that targets all computational steps in a sparse solver rather than narrowing the problem into small kernels (e.g., SpMM, SpMV). We present the implementation details of DeepSparse and demonstrate its merit in two popular eigensolvers, LOBPCG and Lanczos algorithms. We observe that DeepSparse achieves 2× - 16× fewer cache misses across different cache layers (L1, L2 and L3) over implementations of the same solvers based on optimized library function calls. We also achieve 2× - 3.9× improvement in execution time when using DeepSparse over the same library versions.

With the advent of immersive virtual reality (VR) head-mounted displays (HMD), we envision that immersive VR will revolutionize the personal fitness experience in our daily lives. Toward this vision, we present JARVIS, a virtual exercise assistant that is able to provide an immersive and interactive gym exercise experience to a user. JARVIS is enabled by the synergy between Internet of Things (IoT) and immersive VR. JARVIS employs miniature IoT sensing devices removably attachable to exercise machines to track a multitude of exercise information including exercise types, repetition counts, and progress within each repetition in real time. Based on the tracked exercise information, JARVIS shows the user the proper way of doing the exercise in the virtual exercise environment, thereby helping the user to better focus on the target muscle group. We have conducted both in-lab experiments and a pilot user study to evaluate the performance and effectiveness of JARVIS, respectively. Our in-lab experiments with fifteen participants show that JARVIS is able to segment exercise repetitions with an average accuracy of 97.96% and recognize exercise types with an average accuracy of 99.08%. Our pilot user study with ten participants shows statistically significant improvements in perceived enjoyment, competence, and usefulness with JARVIS compared to a traditional machine exercise setting (p < 0.05). Finally, our surface electromyography (sEMG) signal analysis conducted during the pilot user study shows statistically significant improvement in terms of muscle activation (p < 0.01), indicating the potential of JARVIS in providing an engaging and effective guidance for machine exercises.

We demonstrate JARVIS, a novel virtual coaching system based on virtual reality (VR) and Internet of Things (IoT) technologies. It creates a truly immersive gym exercising experience for machine-based strength training and guides users in a highly interactive manner. With these unique advantages, we believe that JARVIS has a potential to revolutionize personal fitness experiences.

Most of the topology control protocols for wireless ad hoc networks focus on minimizing power consumptions while maintaining connectivity. Those protocols are static in nature due to the fact that all the nodes use only a fixed set of (energy efficient) relays. However, using the same set of relays all the time causes some nodes to become heavily loaded creating congestion, unbalanced traffic and high latency in the network. Instead of generating a single topology with fixed relay sets, we propose a distributed algorithm that generates a family of connected topology with (possibly) disjoint relay sets. Thus, by creating different energy aware relay sets of each node the proposed algorithm performs a time-delayed rotation of data forwarding duty among those sets in order to evenly distribute loads in the network. We illustrate the efficiency and efficacy of the proposed algorithm through simulation experiments.