The β-Ga2O3/SiC heterojunction exhibits significant application potential across multiple fields. This work systematically investigates the influence of β-Ga2O3 anisotropy and SiC polarity on interface characteristics by combining different surfaces and terminations of β-Ga2O3 with SiC polar faces. All models exhibit type-II band alignment with valence band offsets (VBOs) larger than 1.8 eV, which is suitable for photodetector applications. Contrary to polarity expectations, most Si-face models generally exhibit VBOs larger than those of their C-face counterparts. The observed anomalies arise from unsaturated C-O bonds within the C-face's interfacial six-membered-ring structure, which introduces band edge states at the interface. Holes from the β-Ga2O3 side will first occupy these states before transferring to SiC, leading to greater band upward shifting at the β-Ga2O3 side and consequently reduced VBOs. By revealing the origin and impact of the underlying mechanisms, this work provides a theoretical basis for band engineering in β-Ga2O3/4H-SiC heterojunctions.

Silicon carbide (SiC) devices possess advantages such as high frequency, high efficiency, and high power density. To enhance device capacity, welded SiC MOSFETs employ a multi-chip parallel packaging format. However, due to variations in chip parameters and packaging parasitic parameters, the current distribution among multi-chip parallel MOSFETs is not entirely uniform. This article models and analyzes a self-developed 6500V/400A SiC MOSFET device. Firstly, a multi-chip parallel device model including internal parasitic parameters is established. Secondly, the device model is calibrated. Finally, a switching circuit with inductive load is built using simulation software to comparatively analyze the impact of auxiliary source lead inductance and source inductance on the parallel current sharing of the multi-chip device. The research results provide reference for device packaging design.

A novel SiC double-trench metal-oxide-semiconductor field effect transistor (MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source trench (MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage V (F) and suppresses the bipolar degradation phenomena. The V (F) of 1.70 V (@I (ds) = -100 A/cm(2)) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET (DT MOS). Meanwhile, the reverse recovery charge Q (rr) of the MT MOS is 58.7% lower than that of the DT MOS at I (load) = 700 A/cm(2), and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches, the MT MOS preserves the same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on breakdown voltage and R (ON,sp) compared to the trench gate MOSFET with planar integrated SBD (ST MOS).

The analysis of bipolar degradation in 18 kV SiC IGBT with constant voltage stress was studied. Its fabrication process as well as testing conditions of IGBT device structure were described. The output characteristics were used for analysis in testing of the degraded devices. In addition, it was revealed that the device with no defects on the surface of the epitaxial layer suffers from unexpected degradation under low voltage stress, while the device with poor performance was completely degraded under high voltage stress. The research results will be a good guidance for controlling defects of high-voltage devices in the process of substrate, epitaxy and chip fabrication.

We studied the effect of linear and interrupted linear cell topologies on the characteristics of 1.2 kV 4H-SiC planar power MOSFETs. These two cell designs both have high breakdown voltages and similar threshold voltages. But the on-resistance for the interrupted linear cell design is reduced by 12 % than that of the linear cell design. The measured reverse-transfer capacitances for the interrupted linear cell is 24 % larger compared to the linear cell at a drain bias of 0.1 V. A trade-off between the static and dynamic electrical characteristics of 1.2 kV SiC power MOSFETs with different cell topologies needs be adjusted in different applications.

The comparison of domestic and foreign studies has been utilized to extensively employ junction termination exten-sion (JTE) structures for power devices. However, achieving a gradual doping concentration change in the lateral direction is diffi-cult for SiC devices since the diffusion constants of the implanted aluminum ions in SiC are much less than silicon. Many previ-ously reported studies adopted many new structures to solve this problem. Additionally, the JTE structure is strongly sensitive to the ion implantation dose. Thus, GA-JTE, double-zone etched JTE structures, and SM-JTE with modulation spacing were reported to overcome the above shortcomings of the JTE structure and effectively increase the breakdown voltage. They pro-vided a theoretical basis for fabricating terminal structures of 4H-SiC PiN diodes. This paper summarized the effects of different terminal structures on the electrical properties of SiC devices at home and abroad. Presently, the continuous development and breakthrough of terminal technology have significantly improved the breakdown voltage and terminal efficiency of 4H-SiC PiN power diodes.

The effect of overlap region for schottky metal and field oxide (ORSMFO) of field limiting rings termination on the reverse breakdown voltage of 6500 V/50A 4H-SiC JBS diodes was studied. Two comparative diodes were designed and fabricated. The reverse breakdown voltage of diodes with 20 mu m ORSMFO improved significantly, which was up to 7000 V at the reverse leakage current of 10 mu A and yield was up to 73 %. The structure simulation implied that the difference of the ORSMFO influenced the electric field strongly. Compared with the simulative terminal structure with 3 mu m and 0 mu m ORSMFO, the electric field intensity of the simulative terminal structure with 20 mu m ORSMFO reduced by about 30 %-50 % near the main junction and the first three field rings.

Short circuit characteristics of 4H-SiC MOSFETs with different channel lengths are studied in this work. The peak drain-source current during the short-circuit period is measured. These results show that short channel devices has lower capability to sustain short-circuit condition. This work found an evident current tail after the gate turning off. Through the investigation with different device design, circuit condition and numeric simulation. The cause of the current tail is found to be due to the increased ionization of electron-hole pair as the junction temperature is elevated at long short-circuit condition.

Annealing treatment has an important effect on the electrical properties of Schottky diodes. In this paper, the effect of Schottky annealing temperature on reverse leakage current of 6500 V 4H-SiC JBS diodes was studied. The reverse leakage current of the diode annealed at 500 degrees C is higher than that of the diode annealed at 450 degrees C. This is because the Schottky barrier height of the diode annealed at 500 degrees C is decreased by 0.08 eV, which leads to a large reverse leakage current. Meanwhile, the Schottky barrier height of the diode annealed at 500 degrees C is decreased more significantly with the increase of measurement temperature, therefore the reverse leakage current increases significantly.

For a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET), both the body diode of the MOSFET and an anti-parallel diode can function as a freewheeling diode that carries reverse current. Selecting a suitable freewheeling method is particularly important to fully exploit the performance of high-voltage SiC MOSFET devices. In this study, based on the 6.5 kV SiC MOSFET and the Schottky barrier diode (SBD) developed by our research group, the dynamic characteristics of the MOSFET body diode, the SBD, and the parallel connection of the two are investigated. In addition, the influence of capacitive current on the dynamic characteristics is analyzed by establishing an equivalent circuit model. Test results show that when compared with the body diode, the SBD has an extremely low reverse recovery current, a lower capacitive current, and better reverse recovery temperature stability. Thus, the SBD is regarded as the most suitable freewheeling diode for the 6.5 kV SiC MOSFET. Finally, a package solution for the 6.5 kV SiC MOSFET and SBD is proposed.

High voltage SiC power devices have been proven as the potential candidates in replacing the Si counterparts to improve the overall power converting efficiency of the power grids and power systems. In this paper, the demonstrations of high voltage materials and devices along with the applications in the power electronic transformer are presented. Through optimizing the temperature and pressure fields, the grown wafer is totally 4H-SiC and no foreign type exists. The FWHM (Full Width at Half Maximum) of the X-ray rocking curve is 23 arcsec, which indicates a high crystalline quality. Moreover, a thick epitaxial layer is then grown on the wafer. The BPD (Basal Plane Dislocation) density of the epitaxial layer is eliminated by converting the BPD to TED (Threading Edge Dislocation) through a proposed doping-induced defect evolution technology. Furthermore, the high voltage SiC MOSFETs with a blocking voltage of over 6.5 kV are fabricated by optimizing the cell and termination structures. The channel region and JFET region are optimized to further improve the device per-formance. The typical current conducting capability of a single MOSFET is up to 25 A and the breakdown voltage reaches 7.8 kV at a leakage current of 10 mu A. The devices are then packaged to form the 6.5 kV/400 A power modules. The current balancing and thermal designs are taken into consideration to improve the reliability of power modules. Finally, the developed SiC modules are applied in a solid state transformer to demonstrate the advantages of SiC devices. The work presented in this article provides an important guide in developing high voltage and high current SiC power devices.

Aiming at the limitation that the parasitic parameters of the existing dynamic test device are large and cannot be accurately measured, a low parasitic parameter dynamic test device is designed in this paper, which can realize the accurate measurement of the dynamic parameters of the high-voltage SiC MOSFET module. The test device consists of a hardware platform and a software system. The hardware platform includes the double-pulse test circuit, measuring instruments, power supply, DSP control device and other modules, and is the main execution unit of the test device. The software platform consists of the host computer and the LabVIEW man-machine interface, which can realize one-button automated testing. The 6.5 kV/400 A SiC MOSFET power module independently developed in China is tested by the test device, and the transient performance of it under different operating junction temperatures is studied. The experimental results have certain reference significance for the design optimization and application of SiC MOSFET under high voltage and high current.

The test of dynamic and static parameters are the necessary step for SiC MOSFET (Silicon Carbide Metal- Oxide-Field-Effect-Transistor) module to be verified after packaging. In this paper, the 6.5kV/100A welding SiC module is selected to test the dynamic and static parameters at room temperature and high temperature successively. The module is packaged by our team with two 6.5kV/50A SiC MOSFET and two 6.5kV/50A SiC SBD (Schottky Barrier Diode) based on 6-inch SiC wafer developed by our company. The influence of temperature on the static and dynamic parameters is analyzed by data extraction, calculating the rate of change and drawing the radar comparison diagram. Combined with the working principle of SiC MOSFET and SiC SBD chip inside the module, the main reason of the change of dynamic and static parameters caused by temperature is studied.

Silicon carbide (SiC) material features a wide bandgap and high critical breakdown field intensity. It also plays an important role in the high efficiency and miniaturization of power electronic equipment. It is an ideal choice for new power electronic devices, especially in smart grids and high-speed trains. In the medium and high voltage fields, SiC devices with a blocking voltage of more than 6.5 kV will have a wide range of applications. In this paper, we study the influence of epitaxial material properties on the static characteristics of 6.5 kV SiC MOSFET. 6.5 kV SiC MOSFETs with different channel lengths and JFET region widths are manufactured on three wafers and analyzed. The FN tunneling of gate oxide, HTGB and HTRB tests are performed and provide data support for the industrialization process for medium/high voltage SiC MOSFETs.

SiC器件具有高温、高压、高频的优异特性,广泛应用于交通、电力等领域,其国产化迫在眉睫.以全球能源互联网研究院有限公司研制的同一批次不同晶圆上的30个1 200 V/20 A SiC MOSFET作为研究对象,通过对比实验分析了测试仪器及方法对国产SiC MOSFET的静态特性参数测试结果的影响.采用标准差、偏度、峰度、偏离度和变异系数量化评估了 SiC MOSFET动、静态特性参数的一致性,发现跨导、漏源极电容、栅源极电容、下降时间和关断延时一致性较好,而导通电阻、阈值电压、栅漏极电容、上升时间和开通延时的一致性较差,从而为后续器件的改进设计提供数据支撑.

This work investigated the integration of Schottky barrier diode (SBD) into SiC MOSFET to address the severe bipolar degradation issue caused by the bipolar conduction through the SiC MOSFET body diode. The impact of key structure parameters on the device performance is studied through numerical simulations. An optimum Schottky contact length is then chosen for fabrication. The fabricated device demonstrates a blocking voltage over 1350V. The conduction ONresistance is 300mΩ. With Titanium as the source Schottky metal, the reverse turn-on voltage of the SiC MOSFET is below 1V, which is 3 times lower than that of the conventional SiC MOSFET. More importantly, with such an integrated SBD, the reverse conduction can be achieved with only unipolar current. Therefore, the bipolar degradation can be prevented to improve long term reliability.

优化设计了电力系统用6.5 kV SiC MOSFET,测得该器件的导通电流为25 A,阻断电压为6 800 V,器件的巴利加优值(BFOM)达到925 MW/cm2.基于感性负载测试电路测试了器件的高压开关瞬态波形.在此基础上,借助仿真软件构建6.5 kV SiC MOSFET芯片级和器件级仿真模型,通过改变器件元胞结构、阱区掺杂浓度、栅极电阻、寄生电感等参数,研究了 6.5 kV SiC MOSFET开关瞬态过程和电学振荡影响因素.结果表明,减小结型场效应晶体管(JFET)宽度有利于提高器件dV/dt能力,而源极寄生电感和栅极电阻是引起栅极电压振荡的重要因素.研究结果有助于分析研究6.5 kV SiC MOSFET在智能电网应用中的开关特性,使得基于SiC MOSFET的功率变换器系统具有更低的损耗、更高的频率和更高的可靠性.

碳化硅器件在高压、高频、高温、大功率、低损耗及抗辐射等方面均比硅基器件拥有巨大优势,可以极大提升电力电子系统的功率、效率、体积及重量等性能指标,在高压输变电、新能源汽车、航空航天、造舰航海等领域具有巨大的应用前景.其电气特性中的动静态特性及高温可靠性作为表征碳化硅功率金属场效应晶体管(metal oxide field-effect transistor,MOSFET)模块性能的必要参数是首先需要分析的环节.然而目前国内对于高压大功率碳化硅MOSFET模块的动静态及高温可靠性参数的测试分析较为贫乏.动静态参数测试是筛选功率模块性能是否达标的必备步骤,可靠性测试是验证模块处于长期高温环境中的极端工作性能,这些测试结果将是反馈优化器件设计和模块封装性能的重要基础,同时对于推动碳化硅功率MOSFET模块的发展和应用具有十分必要的意义.文中旨在较项目组前期4寸碳化硅晶圆制备的芯片封装而成的同等电压等级的碳化硅模块研究的基础上,选取优化芯片设计并在6寸碳化硅衬底上制备而成的碳化硅器件,封装成6500V/50A碳化硅MOSFET模块,并对其进行动静态及高温可靠性测试与分析,验证芯片设计、集成与封装工艺的效果,其最终结果将为项目组后期碳化硅MOSFET芯片设计、集成及封装工艺的进一步优化和改进提供重要参考.

碳化硅(SiC)具有禁带宽、临界击穿场强大、热导率高、高压、高温、高频等优点.应用于硅基器件的传统封装方式寄生电感参数较大,难以匹配SiC器件的快速开关特性,同时在高温工况下封装可靠性大幅降低,为充分发挥SiC器件的优势需要改进现有的封装技术.针对上述挑战,对国内外现有的低寄生电感封装方式进行了总结.分析了现有的高温封装技术,结合新能源电力系统的发展趋势,对SiC器件封装技术进行归纳和展望.

>Dear editor,SiC MOSFET has the advantages of low specific onresistance(Ron,sp), high breakdown voltage(BV), high operating temperature, and low thermal resistance. As a switching device, SiC MOSFET needs an anti-paralleled freewheeling diode(FWD) in many cases. Owing to the wide band gap, the body diode in SiC MOSFET has a drawback of high turn-on voltage(VF) in the reverse conduction [1].