The object of research is the process of hardware/software co-design and computational load distribution for digital signal processing (DSP) algorithms in heterogeneous systems-on-chip (SoC). The problem solved in this work is the lack of effective methods for distributing computational functions at the early design stages of architectures combining a processing system (PS) and programmable logic (PL). Unlike approaches relying on intuitive distribution or a full synthesis cycle, causing hardware overhead or timing violations, a hardware/software co-design method for DSP algorithms which accounts for the technological parameters of the SoC platform and enables analytical selection of the optimal implementation route at the system level, has been developed. A computing distribution model for the PS and PL parts is proposed, integrating platform characteristics, design object parameters, and specification constraints. A system of sub-criteria has been defined to minimize algorithm execution time under strict platform constraints. Based on these criteria, quantitative thresholds have been established to choose between software, hardware, or hybrid implementation routes, depending on the size of the design object. Using the Zynq-7000 as an example, it is proven that software implementation on the PS side is effective for small- and medium-sized objects, while transitioning to the PL part is critical for large-scale objects. It was established that transitioning from native code to high-level synthesis (HLS) and structural C code optimization strategies (specifically the C2 method) improves system metrics, cutting execution time in half while reducing resource utilization by 30%. The method is recommended for designing embedded real-time DSP systems, processing media streams, analyzing high-dimensional sensor data, and creating intelligent decision support systems.

The implementation of the Fast Fourier Transform (FFT) algorithm and finite impulse response (FIR) filter on the Xilinx ZYNQ-7000 System-on-Chip (SoC) platform was considered. A comparison and analysis of the timing characteristics and memory consumption during the FFT algorithm implementation with different lengths using specialized libraries and FIR filter implementation on the Processing System part of the SoC have been performed. The FFT and FIR filter algorithms were implemented in the programming language C using Vivado/Vitis tools. Among various implementation methods for FFT and FIR on the PS part, the best performance was achieved using the NE10 library on the platform SoC Xilinx ZYNQ-7000.

The subject matter of the work is the impact of code optimization methods of highly intensive algorithms, used in digital signal processing, on hardware costs and performance when implemented on different platforms. The goal of the work is to conduct a comparative analysis of the impact of the effects of three C-code optimization approaches: loop unrolling, switching to fixed-point arithmetic, and their combinations, on performance and hardware costs when implementing matrix multiplication, fast Fourier transform, and wavelet transform algorithms using high-level synthesis (HLS) tools on system-on-chip (SoC) platforms, personal computers (PCs), and single-board computers. The following tasks were solved in the article: implementation of highly intensive algorithms based on selected hardware platforms and using HLS; comparison of execution time of algorithms with and without different optimization methods; comparison of hardware costs for algorithms’ implementations with and without different variants of optimization; formulate conclusions about the impact of different C-code optimization methods on performance and hardware costs on different target platforms. The following methods were used: C/C++ code optimization methods, diagnostic experiments using high-level synthesis tools to implement digital signal processing algorithms on the selected hardware platform, and statistical data collection using Python. The following results were obtained: for algorithms based on arithmetic operations, code optimization provided up to 30% reduction in execution time on ARM platforms. For algorithms based on the Fourier transform, complex optimization reduced execution time by up to 90% on processor devices. For programmable logic (FPGA), none of the optimization methods provided a significant execution acceleration. However, the transition to fixed arithmetic reduced hardware costs by 40–80% regardless of the algorithm type. Conclusions. The choice of a C code optimization strategy significantly impacts the efficiency of algorithm implementation on processor architectures. In contrast, optimizing the data types used plays a key role for FPGAs. In contrast, for FPGAs, optimizing the data types used plays a key role.

The implementation of the Fast Fourier Transform (FFT) algorithm on the Xilinx ZYNQ-7000 SoC system-on-chip technology platform is considered. The time and hardware costs for implementing the FFT algorithm for different options for its length on the PS part of the SoC using specialized libraries and the implementation of this algorithm on the PL part of the SoC using the IP-core from the Xilinx repository are compared. The implementation of the FFT algorithm is performed in the C programming language using the Vivado/Vitis tools. The best performance among different ways to implement the FFT algorithm was shown by using the standard Xilinx HLS FFT IP IP for the PL part of the SoC Xilinx ZYNQ-7000. Fig.: 6, Refs.: 13 titeles.

Об’єктом дослідження є процедури автоматизованого проєктування та аналізу алгоритмів цифрового оброблення сигналів на технологічній платформі SoC. Предмет вивчення – моделі, методи та процедури проєктування та оптимального вибору компонентів SoC для реалізації алгоритмів цифрового оброблення сигналів аудіоспектра. Метою дослідження є розроблення моделей та процедур для визначення можливостей компромісного розподілу обчислень алгоритмів оброблення сигналів у циклі автоматизованого проєктування на технологічній платформі SoC за критерієм продуктивності й доцільності використання апаратної та програмної реалізації алгоритмів. У статті розв’язуються такі завдання: розгляд процедур взаємодії процесорного ядра з програмованою логікою у складі систем на кристалі; розвиток процедур автоматизованого проєктування та аналізу систем оброблення сигналів із використанням мов програмування та мов опису апаратури для реалізації вбудованих систем. Упроваджуються такі методи: імплементація алгоритмів цифрового оброблення сигналів мовою програмування С та інструментів високорівневого синтезу для реалізації IP-блоків, діагностичний експеримент способом генерації тестових патернів сигналів та аналіз результатів оброблення на виході системи. Досягнуті результати. На основі аналізу процедур взаємодії процесорного ядра та програмованої логіки на обраній платформі SoC спроєктовано модель системи оброблення сигналів аудіоспектра. Практичну реалізацію виконано на базі стеку інструментальних засобів САПР Vivado/Vitis/Vitis HLS. Проведено верифікацію запропонованої моделі з використанням програмованого генератора тестових сигналів та аналізу отриманих характеристик цифрових фільтрів на виході системи. Висновки. У статті проаналізовано принципи проєктування вбудованих систем оброблення інформації, що реалізуються в системах на кристалі. Розглянуто принципи побудови та аналізу систем цифрового оброблення сигналів на базі систем на кристалі, що містять програмовану логіку та процесорну частину. Розроблені методи апробовано на алгоритмах CIC- та FIR-фільтрів на технологічній платформі SoC FPGA сімейства ZYNQ-7000 фірми Xilinx.

The subject of this paper is the analysis of DSP algorithm implementations based on HLS synthesis and SIMD instructions acceleration on the SoC hardware platform. The goal of this article is to analyze various FIR filter software and hardware implementations based on the technological platform SoC ZYNQ 7000 while obtaining metrics of hardware resource consumption, power efficiency, and execution performance. The tasks are as follows: determine the ways of implementing algorithms; choose the analysis criteria for multivariate experiment; implement algorithms using SIMD instructions on the ARM part of the given SoC; implement algorithms using High-Level Synthesis for the FPGA part; and measure and obtain the results for each signal topology. The used methods: High-Level Synthesis, optimization techniques based on vector instructions, and multivariate experiment analysis. The following results were obtained: for the given criteria and metrics. The FIR filter was implemented on the ZedBoard development platform with SoC ZYNQ 7000. The data were obtained from post-synthesis power analysis and dynamic SoC consumption using tools from Xilinx and Analog Devices. The corresponding IP blocks were implemented using High-Level Synthesis. The experiment was completed to obtain execution performance metrics. Conclusions. The scientific novelty of the obtained results is summarized as follows: the competitor analysis was performed for the set of implementations of the given algorithms deployed on the ZYNQ platform using both SIMD instructions and several HLS-based topologies for the FPGA-offload execution strategy. The analysis of the multivariate experiment was also completed for selected criteria, power consumption, filtering speed (inverse value – delay), and the amount of hardware costs as a percentage of the used resources.

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Предметом дослідження в статті є моделі, методи та процедури проєктування та самодіагностики автоматних моделей пристроїв логічного керування, реалізованих в SoC. Об’єкт роботи – процедури автоматизованого проєктування та діагностування цифрових пристроїв на технологічній платформі SoC. Метою дослідження є розроблення моделей і процедур проєктування та самотестування в циклі автоматизованого проєктування автоматних систем логічного управління на технологічній платформі SoC, що суттєво підвищить надійність їх функціювання. У статті вирішуються такі завдання: розгляд процедур взаємодії процесорного ядра з програмованою логікою у складі SoC; удосконалення процедур проєктування та тестування програмно-апаратних систем на основі SoC; подальший розвиток процедур автоматизованого проєктування, верифікації та діагностування кіберфізичних систем логічного управління з використанням мов програмування та мов опису апаратури; реалізація процедури апаратного самотестування керуючих автоматів на технологічній платформі SoC. Упроваджуються такі методи: синтез керуючих автоматів на основі графових моделей, імплементація моделей керуючих автоматів мовою програмування С з використанням автоматного шаблону, діагностичний експеримент способом обходу графа переходів автомата. Досягнуті результати. На основі аналізу процедур взаємодії процесорного ядра та програмованої логіки на обраній платформі SoC спроєктовано модель кіберфізичної системи логічного управління. Практичну реалізацію виконано на базі стеку інструментальних засобів САПР Vivado/Vitis/Vitis HLS. Реалізовано метод апаратного самотестування керуючих автоматів на технологічній платформі SoC ZYNQ-7000. Висновки. У статті проаналізовано принципи проєктування вбудованих кіберфізичних систем, що реалізуються в системах на кристалі. Розглянуто принципи побудови систем верифікації та вбудованої самодіагностики систем на кристалі, що містять програмну й апаратну частини. Розроблені методи апробовано на моделі пристрою логічного керування світлофором на технологічній платформі SoC FPGA сімейства ZYNQ-7000 фірми Xilinx. Керуючий автомат Мура реалізовано у блоці PL мовою програмування С, а операційний автомат – у блоці PS. Під час організації процесу самодіагностики здійснено неруйнівний діагностичний експеримент способом обходу всіх дуг графа переходів, починаючи з початкової вершини. Тестером у цьому разі був операційний автомат, еталонні логічні та часові значення якого зберігалися в пам’яті блока PS. Візуальне спостереження за виконанням діагностичного експерименту здійснювалося за допомогою панелі світлодіодів плати ZedBoard.

The subject of research in this article is models, methods, and procedures for designing and self-diagnosing automated models of logic control devices implemented in SoCs. The object of work is the procedures for automated design and diagnosis of digital devices on the SoC technology platform. The aim of the study is to develop models and procedures for designing and self-testing in the cycle of automated design of automatic logic control systems on the SoC technology platform, which will significantly increase the reliability of their operation. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of the SoC; improvement of the procedures for designing and testing software and hardware systems based on SoC; further development of procedures for automated design, verification, and diagnosis of cyber-physical logic control systems using programming languages and hardware description languages; implementation of the procedure for hardware self-testing of control automata on the SoC technology platform. The following methods are implemented: synthesis of control automata based on graph models, implementation of control automata models in the C programming language using an automata template, diagnostic experiment by traversing the automata transition graph. Results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of a cyber-physical logic control system was designed. The practical implementation was carried out on the basis of the Vivado/Vitis/Vitis HLS CAD toolkit. The method of hardware self-testing of control automata on the technological platform of SoC ZYNQ-7000 was implemented. Conclusions. The article analyzes the principles of designing embedded cyber-physical systems implemented in system-on-chip. The principles of building verification systems and embedded self-diagnostics of system-on-chip systems containing software and hardware are considered. The developed methods are tested on a model of a traffic light logic control device on the SoC FPGA platform of the ZYNQ-7000 family by Xilinx. The Moore's control automaton is implemented in the PL block in the C programming language, and the operational automaton is implemented in the PS block. During the organization of the self-diagnosis process, a non-destructive diagnostic experiment was performed by traversing all arcs of the transition graph, starting from the initial vertex. In this case, the tester was an operational automaton, the reference logic and time values of which were stored in the memory of the PS unit. Visual observation of the diagnostic experiment was carried out using the LED panel of the ZedBoard board.

The analysis of existing platforms and tools for designing systems on chip is given. The variants of soft-processor architectures that are relevant at the current moment are considered, prospective directions of research and integration into embedded systems are determined. The overview of solutions based on the RISC-V architecture and softcore processors based on them was conducted. The existing solutions from FPGA vendors to realize the possibilities of partial reconfiguration of the system are considered. The typical problems encountered in the design of embedded systems and possible tools which can be used for requirements analysis are presented.

The work is devoted to the topical problem at the intersection of communications theory, digital electronics and numerical analysis, namely the study of image processing methods implementation time on different architectures of computational devices, which are used for software and hardware acceleration. The subject of this article is the investigation of reconfigurable FPGA processing systems in the image processing area. The goal of this work is to create a reconfigurable FPGA-based image processing system and compare it with existing processing architectures. Task. To fulfill the requirements of this work, it is necessary to prepare a practical experiment as well as theoretical research of the proposed architecture; to investigate the process of creating a ZYNQ SoC-based image processing system; and to develop and benchmark the speed of execution for the given set of algorithms with the specific range of the picture resolution. Methods used: FPGA simulation, C++ parallel programming with OpenMP, NVIDIA CUDA, performance analysis tools. The result of this work is the development of a resilient SoC Zynq7000–based computing system with programmable logic and the possibility to load images to FPGA RAM using the resources of ARM core for further processing and output via HDMI video interface, which enables the change of PL configuration at any time during the processing process. Conclusions. The efficiency of the FPGA approach was compared with a parallel image processing method implementation with OpenMP and CUDA. An overview of the ZYNQ platform with specific details related to media processing is presented. The analysis of algorithm speed testing findings based on various outputs proved the advantage (of over 60 times) of hardware acceleration of image processing over software analogs. The obtained results may be used in the development of embedded SoC-based solutions that require acceleration of big data processing. Also, the achieved findings can be used during the process of finding a suitable embedded platform for a certain image-processing task, where high data throughput is one of the most desired requirements.

The article is dedicated to the problem of parallel computing on multicomputer accelerated data processing systems, namely on cluster computing systems, which consist of many independent computers and the network that connects them. The computing components of the cluster being designed are four single-board Raspberry Pi 3B+ computers. Raspbian Buster is used as the operating system for the designed cluster. The cluster system uses a SD memory card as a disk array and does not have the ability to connect nodes to the only one drive, so the topology of cluster pairs uses a distributed access topology that allows each memory disk to connect to only one cluster node. Messaging between processes is provided by the MPI interface. One of the main advantages of the cluster is the ability to scale, which, in the case of increasing computational load, leads to increased acceleration and efficiency of parallel computing. The performance of the created computing cluster based on four single-board Raspberry Pi 3B+ computers was tested on the problem implementation of the large matrices accelerated multiplication, as matrix operations are the basis of scientific and engineering calculations, and are used in mathematical modeling of various processes, phenomena and systems.

The work is devoted to the topical problem at the intersection of communications theory, digital electronics and numerical analysis, namely the study of image processing methods implementation time on different architectures of computational devices, which are used for software and hardware acceleration. The subject of this article is the investigation of reconfigurable FPGA processing systems in the image processing area. The goal of this work is to create a reconfigurable FPGA-based image processing system and compare it with existing processing architectures . Task. To fulfill the requirements of this work, it is necessary to prepare a practical experiment as well as theoretical research of the proposed architecture; to investigate the process of creating a ZYNQ SoC-based image processing system; and to develop and benchmark the speed of execution for the given set of algorithms with the specific range of the picture resolution. Methods used: FPGA simulation, C++ parallel programming with OpenMP, NVIDIA CUDA, performance analysis tools. The result of this work is the development of a resilient SoC Zynq7000–based computing system with programmable logic and the possibility to load images to FPGA RAM using the resources of ARM core for further processing and output via HDMI video interface, which enables the change of PL configuration at any time during the processing process. Con-clusions. The efficiency of the FPGA approach was compared with a parallel image processing method implementation with OpenMP and CUDA. An overview of the ZYNQ platform with specific details related to media processing is presented. The analysis of algorithm speed testing findings based on various outputs proved the advantage (of over 60 times) of hardware acceleration of image processing over software analogs. The obtained results may be used in the development of embedded SoC-based solutions that require acceleration of big data processing. Also, the achieved findings can be used during the process of finding a suitable embedded platform for a certain image-processing task, where high data throughput is one of the most desired requirements.

According to the growing complexity of tasks, which embedded systems should solve, there arises a need to use Real-Time Operation Systems (RTOS). However, RTOS usage and implementation require a set of restrictions for a system, especially on the memory usage and time delays occurrence. The available implementations of coroutines neither cross-platform solutions nor accessible without a third-party library. The article proposes a model of cross-platform coroutine usage from C + + 20 for embedded systems programming and lightweight cooperative multitasking implementation. The proposed model contains the improved minimal scheduler without priorities mechanism and tasks descriptors. The model of coroutines usage for resource-constrained systems is developed. The task inside the model is presented as a coroutine, which can communicate with available coroutines, call them, or be suspended. Also, the minimal primitives of coroutines usage for cooperative multitasking, architecture decisions, and non-blocking data transmission were implemented. For the experimental research, the following list of program components was implemented in the proposed model: cooperative coroutines scheduler, tasks for data transmission, and awaitable type prototypes. The testing and analysis were completed on the chosen microcontroller (MCU). The perspective of coroutines usage on resource-constrained systems was shown in the research based on obtained results of FLASH and RAM consumption.

Mass transit systems are present in cities worldwide. To provide satisfactory level of surface public transportation quality and to prevent unnecessary injurious time competitions between high-capacity transit vehicles and private cars, transit signal priority techniques were considered to introduce in traffic light controller. Transit networks configurations were analyzed, and appropriate methods of transit vehicles motion management were introduced in the developed model of adaptive real-time transit signal control system.

The aim of the work is to analyze hardware costs of ensuring the testability of finite state machines with various options for organizing an additional transition between FSM's states depending on the presence of an unconditional transition, a conditional transition, and the absence of transitions between states of analyzed FSM. The conclusion on additional hardware costs is made on the basis of a comparison of synthesis results of testable HDL-models by means of CAD FPGA. The paper solved the problem of computer-aided design of testable control FSM based on the application of methods for setting FSM in a given state. The best way to organize additional transitions during setting of control FSM in an arbitrary state is the transition for which the total hardware cost estimate for the excitation functions is minimal, taking into account the coding of FSM's states.

Methods of hardware implementation of event-driven timed control FSM were considered in the article. Classification of timed control FSM into active and passive by the method of processing input signals, and into Moore and Mealy models by the method of generating output signals were given. Timing parameters are implemented by the counter of FSM’ clock cycles. Timed FSM models are presented in the VHDL hardware description language in the form of automata pattern. Behavioral simulation of proposed models, synthesis and implementation in FPGA, as well as simulation after implementation using CAD Xilinx ISE 14.7 were performed.

Modern highly technological production puts forward new requirements and approaches to the implementation of the Industry 4.0 concept. To achieve this, it is necessary to develop a cyber-physical production system that would make it possible to fully take into consideration all the factors of the actual production system. All solutions must pursue the global goal of making the best use of production time and resources, as well as meet the "Lean Production" concept. Existing ISO-95, 5C, and 8C cyber-physical production systems (CPPS) reference architectures cannot provide clearly expressed systematization and detailing. Such systems are a set of general recommendations that show the interaction processes among the physical and cyber-components of CPPS. This paper reports a new approach to the systemic representation of the processes for managing the development of complex cyber-physical production systems in the face of today's threats. We have suggested a systemic representation of automating the process of managing the development of complex CPPS. Modern threats to the cyber-physical and information and communication systems (ICS) have been considered, which underlie CPPS. An architectural-logical model, as well as methods for automating the CPPS development process management, have been developed. This could help build a logical relationship from the initial "target" stage to the process of obtaining "management algorithms" at each level and stage of CPPS development as a symbiosis of physical and cyber-components. The devised CPPS development process management model provides an opportunity to propose a group of mathematical models and methods that logically link all development stages into a single "rigid" hierarchical sequence. This makes it possible to build a single information space with a set of complex CPPS development methodology. The proposed solutions could enable the development of an automated system to manage the process of the development of complex CPPS

The work is dedicated to verification of automatic logic control systems by analyzing the correctness of state diagrams of control finite state machines which are represented in the form of the code in the hardware description language. As a method for state diagram analysis the, it is proposed to use the concept of orthogonality, as a system of incompatible events. Analysis of the correctness is carried out by analysis the results of behavioral modeling and logical synthesis using CAD tools.