Toward new research directions in computer science.

Microcontrollers (MCUs) for the Internet-of-Things (IoT) are powerful and versatile computing platforms, which may be hard to program correctly and efficiently; power performance is particularly important. We inestigate automatic methods to detect software performance anti-patterns for this class of systems, so as to help the software developer with power-related aspects. We use a virtual prototype, i.e., we execute the real object code on a simulated model of the hardware platform, given as a transaction-level model (TLM) augmented with dedicated monitors. We study two cases taken from an industrial example, and show that our method can help detect patterns that would be difficult to detect statically, even when the source code is available, because they involve the state of the hardware and the timing of operations.

—Maintenance has long been a predominant activity in the industrial sector. Measuring and analyzing physical signals on the machines allows to provide a diagnosis on their health state. The more recent Health Monitoring Systems (HMS) allow to optimize the maintenance operations by performing preventive maintenance. The existing HMS are based on various signal-processing algorithms applied to vibration data gathered during flights, in order to compute health indicators. The computation of the indicators is done on-ground, once a full data set has been offloaded. In this paper, we report on experiments made to turn these on-ground computations into on-board real-time computations , using a many-core processor. There are two main issues to be addressed: (i) the management of the flow of inputs from sensors; (ii) the (hopefully tolerable) errors we make when transforming an on-ground algorithm that can treat data globally, into an on-board real-time algorithm that is necessarily incremental. We show that the error is indeed acceptable.

Hard real-time (HRT) video systems require admission control decisions that rely on two factors. Firstly, schedulability analysis of the datadependent, communicating tasks within the application need to be carried out in order to guarantee timing and predictability. Secondly, the allocation of the tasks to multi-core processing elements would generate different results in the schedulability analysis. Due to the conservative nature of the state-ofthe-art schedulability analysis of tasks and message flows, and the unpredictability in the application, the system resources are often under-utilised. In this paper we propose two blocking-aware dynamic task allocation techniques that exploit application and platform characteristics, in order to increase the number of simultaneous, fully schedulable, video streams handled by the system. A novel, worstcase response time aware, search-based, static hard real-time task mapper is introduced to act as an upper-baseline to the proposed techniques. Further evaluations are carried out against existing heuristic-based dynamic mappers. Improvements to the admission rates and the system utilisation under a range of different workloads and platform sizes are explored. 2012 ACM Subject Classification On-chip resource management

The following topics are dealt with: embedded software; software models, programming languages, and verification methods; time-aware instrumentation; and nonlinear systems.

Many techniques and tools exist to estimate the power consumption and the temperature map of a chip. These tools help the hardware designers develop power efficient chips in the presence of temperature constraints. For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet. However, after the hardware is defined, the embedded software can still have a significant influence on the power consumption; i.e., two implementations of the same application can consume more or less power. Moreover, the actual software power manager ensuring the temperature constraints, usually by acting dynamically on the voltage and frequency, must itself be validated. Validating such power management policy requires a model of both actuators and sensors, hence a closed-loop simulation of the functional model with a non-functional one. In this paper, we present and compare several tools to simulate the power and thermal behavior of a chip together with its functionality. We explore several levels of abstraction and study the impact on the precision of the analysis.

SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of loose-ordering to specify when components interact with each other and we propose a set of patterns to capture this notion in assertions.This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL.

A recent microprocessor architecture breakthrough provides a many-core processor that offers timing guarantees. It gives us an opportunity to study its applicability to avionics systems. We select an avionics function that requires both high processing power and some response time guarantees. The Helicopters Health Monitoring System (HMS) performs signal processing on vibration data, to raise some alerts for the operating crew. The computation requires a high processing bandwidth and the alerting requires a bounded response time. These characteristics makes the HMS a good candidate for an experiment in implementing avionics functions on a many-core processor.

In embedded systems, controlling a shared resource like the bus, or improving a property like power consumption, may be hard to achieve when programming device drivers individually. There is a need for global resource control, taking decisions based on a centralized view of the devices' states. In this paper, we study power consumption in sensor networks, where the nodes are small embedded systems powered by batteries. We concentrate on the hardware/software architecture of a node, where significant gains can be achieved by controlling the consumption modes of the various devices globally. The architecture we propose involves a simple adaptation of the application level, to communicate with the hardware via a control layer. The control layer itself is built from a set of simple automata: the drivers of the devices, whose states correspond to power consumption modes, and a controller that enforces global properties. All these automata are programmed using a synchronous language, whose compiler performs static scheduling and produces a single piece of C code. We explain the approach in details, demonstrate its use with either Contiki or a traditional multithreading operating system, and report on our experiments.

Modern systems-on-chips need sophisticated power-Management policies to control their power consumption and temperature. These power-management policies are usually implemented partly in software, with hardware support. They need to be validated early, hence power and temperature-aware simulation techniques at the system-level need to be developed. Existing approaches for system-level power and thermal analysis usually either completely abstract the functionality (allowing only simple scenarios to be simulated), or run the functional simulation independently from the non-functional one. The approach presented in this paper allows a coupled simulation of a SystemC/TLM model, possibly including the actual embedded software, with a power and temperature solver such as ATMI or the commercial tool ACEplorer. Power and temperature analysis is done based on the stimuli sent by the SystemC/TLM platform, which in turn can take decisions based on the non-functional simulation.

Modern systems-on-chips need sophisticated power-Management policies to control their power consumption and temperature. These power-management policies are usually implemented partly in software, with hardware support. They need to be validated early, hence power and temperature-aware simulation techniques at the system-level need to be developed. Existing approaches for system-level power and thermal analysis usually either completely abstract the functionality (allowing only simple scenarios to be simulated), or run the functional simulation independently from the non-functional one. The approach presented in this paper allows a coupled simulation of a SystemC/TLM model, possibly including the actual embedded software, with a power and temperature solver such as ATMI or the commercial tool ACEplorer. Power and temperature analysis is done based on the stimuli sent by the SystemC/TLM platform, which in turn can take decisions based on the non-functional simulation.

Modern systems-on-a-chip are equipped with power architectures, allowing to control the consumption of individual components or subsystems. These mechanisms are controlled by a power-management policy often implemented in the embedded software, with hardware support. Today's circuits have an important static power consumption, whose low-power design require techniques like DVFS or power-gating. A correct and efficient management of these mechanisms is therefore becoming non-trivial. Validating the effect of the power management policy needs to be done very early in the design cycle, as part of the architecture exploration activity. High-level models of the hardware must be annotated with consumption information. Temperature must also be taken into account since leakage current increases exponentially with it. Existing annotation techniques applied to loosely-timed or temporally-decoupled models would create bad simulation artifacts on the temperature profile (e.g. unrealistic peaks). This paper addresses the instrumentation of a timed transaction-level model of the hardware with information on the power consumption of the individual components. It can cope not only with power-state models, but also with Joule-per-bit traffic models, and avoids simulation artifacts when used in a functional/power/temperature co-simulation.

The description of the work to be done will be detailed later. Feel free to contact for more details if you are interested. The general context: using synchronous languages and tools to program the low-level software of a node used in a sensor network. A sensor network is made of a set of small nodes, each one being an embedded system: there are scarce resources (memory, computing power, energy consumption), and the development of the software depends a lot on the hardware. The existing (...)

This session is dedicated to Paul Caspi. It is made of five talks, each of them addressing one aspect of Paul Caspi's contributions to the development of safe embedded software and systems: synchronous languages and models, the implementation of synchronous languages, the relation between functional and synchronous languages, the relation between continuous and discrete models, and the definition of embedded software and systems master curricula. This session is only a selection of recent work; Paul Caspi also worked on dependability and fault-tolerance, code distribution, and formal verification with theorem provers.

The ability to perform power estimation early in the design flow is becoming more and more critical as power optimization requirements grow. For now, standalone power simulators allow such estimation, based on typical stimuli described in a use-case scenario. We propose a co-simulation of SystemC TLM platforms with a Power model. This way, the Power model benefits from more realistic stimuli. In addition, it is possible to provide real-time information from the Power model back to the SystemC TLM simulation, such as temperature values.

SystemC est une extension du langage C++, definissant une bibliotheque de classes C++ utilisee pour decrire des modeles de systemes sur puces a differents niveaux d'abstraction. Le niveau de description transactionnel (TLM) permet d'executer le logiciel embarque sur un prototype virtuel du materiel tres tot dans le flot de conception. Le modele d'execution defini dans la specification officielle (standard IEEE-1666) a ete pense pour des simulations sur machine monoprocesseur, c'est-a-dire que les processus (...)

AreaCast est un mecanisme d'adressage logique dans un voisinage visant a ameliorer la robustesse a tout type de protocole unicast. AreaCast se base sur la notion de relai implicite tandis que le relayage unicast se base sur le choix explicite du relais. Tout en etant independant du protocole de routage choisi, AreaCast utilise des informations topologiques et de routage pour permettre une communication par zone : un nœud relai explicite choisi comme prochain saut par la couche routage et k nœuds relais implicites qui s'auto-selectionnent en fonction de leur proximite au nœud relai explicite. Ce mecanisme utilise la sur-ecoute pour exploiter la communication de type broadcast inherente aux transmissions sans fil. Sans changer le protocole de routage ni echange de paquets supplementaires, AreaCast permet de contourner dynamiquement un nœud defectueux ou un lien instable. Les resultats de simulation, modelisant finement la consommation energetique, montrent qu'AreaCast ameliore significativement le taux de livraison tout en etant un bon compromis entre efficacite et consommation energetique.

To provide for reliability in Wireless Sensor Networks (WSNs), Medium Access Control (MAC) protocols must be adapted by mechanisms taking cross-layer approaches into account. In this article, after introducing existing MAC protocols, we describe AreaCast, our protocol, which is designed for enhancing reliability in WSNs. AreaCast is a MAC layer protocol independent of the routing layer, but uses only local topological and routing information to provide a communication by area instead of a traditional, node-to-node communication (i.e., unicast). In AreaCast, a source node addresses a set of nodes: an explicit relay node chosen as the next hop by a given routing protocol, and three other implicit relay nodes. The neighboring nodes select themselves as implicit relays according to their distance from the explicit relay node. This mechanism uses overhearing to take advantage of the inherent broadcast nature of wireless communications. Without changing the routing protocol, AreaCast is able to dynamically avoid a byzantine node or an unstable link, allowing to benefit from the inherent topological redundancy of densely deployed sensor networks. Simulation results show that AreaCast significantly improves the packet delivery rate while having a good reliability-energy consumption trade-off.