Transition metal dichalcogenides (TMD) are a fertile playground to study the interactions between charge carriers and external magnetic fields. Van der Waals interlayer interactions enable the investigation of magnetotransport as a function of the different numbers of TMD layers. Here, we demonstrate unsaturated large magnetoresistance (MR) in MoS2 crystals by using a field-effect transistor geometry to tune charge carrier density. Our work shows that the device can be operated in a given regime that allows reaching a maximum MR of 680% at 1.8 K without any sign of saturation. The device exhibits a higher sensitivity to magnetic fields when operating in the subthreshold regime than in its on-state. Our work suggests that this effect stems from a change in the energy of the conducting states as observed by monitoring the threshold voltage shift. Notably, the magnitude of such a shift strongly decreases with temperature and number of layers. By means of Density Functional Theory calculations, we confirm that the origin of such a large MR is not the Lorentz force affecting band-like transport, but rather, an interaction that affects the electronic properties of mid-gap states in MoS2 that are dominating the charge transport at low temperature. This work demonstrates that controlling the charge density in the channel and the transport mechanism leads to engineering of the magnetic sensitivity in 2D materials.

Geometry is a critical factor in radio frequency design that directly affects the performance and efficiency of RF components and systems. The characteristic impedance and the propagation constant of transmission lines are affected by the conductor width, spacing and the dielectric properties. In addition, performance metrics such as insertion loss and bandwidth of microwave filters are also affected by the geometric configuration of resonant elements. This article explores the use of a non-commercial inkjet printer prototype to fabricate high-frequency devices with microscale precision, achieving high-resolution gaps, uniform spacing as small as 9 μm, conductor widths of 50 μm, and a filter that operate at frequencies up to 50 GHz. The chosen substrate is paper as a sustainable, environmentally friendly and flexible platform, that offers adaptability for RF applications in dynamic environments. The design, fabrication and measurements of coplanar waveguides (CPW) transmission lines and passband filter operating at a central frequency of 25 GHz are presented. The performance of the printed filters was studied with respect to the printing and annealing conditions, and it was compared to equivalent filter designs printed on PET substrate.

ABSTRACT The widespread adoption of interconnected architectures, ranging from cloud systems to energy‐limited IoT and edge nodes, is redefining the challenges of hardware security, where trust must be physically anchored in the hardware itself, minimizing reliance on stored digital keys or power‐hungry post‐processing. True Random Number Generators and Physical Unclonable Functions constitute the fundamental building blocks for secure entropy generation and device authentication. CMOS‐based implementations have reached a high level of maturity, achieving remarkable progress in integration, stability, and scalability through sophisticated circuit‐level design strategies. However, further improvements are increasingly constrained by the limited physical entropy available within silicon‐based technologies. In contrast, emerging materials and device platforms, such as resistive and ferroelectric memories, 2D semiconductors, and electrolyte‐gated transistors offer richer stochastic dynamics and intrinsic variability, providing new degrees of freedom for entropy harvesting. This review surveys recent advances in this rapidly evolving field, emphasizing the interplay among material physics, device behavior, and circuit design, and highlights unified architectures that co‐generate entropy and identity within a single chip, leading to secure and energy‐efficient hardware for future IoT and edge platforms.

The growing demand for energy-efficient computing in artificial intelligence requires novel memory technologies capable of storing and processing information. Memristors stand out in thanks to their ability to store information, mimic synaptic behavior and support in-memory computing architectures while requiring minimal active areas and energy consumptions. Here is presented a scalable and cost-effective approach to fabricate Ag/MoS2/Au memristors as resistive switching memory devices by combining roll-to-roll mechanical exfoliation of two-dimensional materials with inkjet printing. These devices exhibit reliable non-volatile switching behavior attributed to the formation and dissolution of metallic conductive filaments within the MoS2 layer, with high resistance ratios and robust retention times. A fully-connected neural networks is simulated using quantized weights mapped onto a virtual memristor crossbar array demonstrating that classification tasks can be performed with high accuracy even with limited bit-width precision, highlighting the potential of these devices for energy-efficient, high-throughput AI hardware.

Counterfeiting is a growing global challenge with significant economic and social implications. Physical Unclonable Functions (PUFs), exploiting manufacturing randomness to generate unique and unclonable identifiers, have emerged as a promising solution for secure authentication. This study presents a novel, scalable method for fabricating inkjet-printed PUFs by exploiting the randomness of ink droplet deposition on substrates such as paper. By optimizing geometric features, the proposed system ensures high uniqueness, reliability, and bit uniformity. The PUFs also exhibits excellent durability, maintaining performance under mechanical stress and chemical exposure. Furthermore, the system incorporates a low-cost imaging setup and advanced positional markers, enabling fast and accurate database validation. This work establishes a robust and low-cost route to PUFs that can be interrogated with consumer-grade devices, making them suitable for various anticounterfeiting applications, including supply chain security and luxury goods authentication.

Hopping transport, characterized by carrier tunneling between localized states, is a key mechanism in disordered materials such as organic semiconductors, perovskites, nitride alloys, and two-dimensionalmaterial- (2DM) based inks. Two main regimes are typically observed-variable-range hopping and nearest neighbor hopping-with a transition between them upon temperature variation. Despite numerous experimental observations, the modeling of this transition remain insufficiently explored and not fully understood. In this work, we present an in-house Monte Carlo random-resistor-network-based simulator capable of capturing both hopping-transport regimes. We demonstrate how material properties that define the network, such as localization length and the spatial and energetic distribution of sites, determine the dominant transport regime. The simulator has been successfully validated against experimental data, showing excellent agreement, reproducing the transition from one regime to the other and accurately capturing one-dimensional, two-dimensional, and three-dimensional variable-range hopping behavior, providing both a theoretical framework for interpreting experiments and a powerful tool for studying transport mechanisms.

Two-dimensional semiconductors are potential channel materials for future scaled complementary transistor technologies due to their high carrier mobility and strong immunity to the short-channel effect. However, the electrical performance of p-type transistors is still far below that of their n-type counterparts. Here we report high-performance p-type monolayer tungsten diselenide transistors with a hole mobility of 137 cm(2) V-1 s(-1) and a contact resistance of approximately 560 Omega mu m at room temperature. Our approach uses an industry-compatible and tunable oxygen-incorporated technique to heal the defect states. A scaled p-type monolayer tungsten diselenide transistor with a channel length of 45 nm exhibits an on-state current of 1,245 mu A mu m(-1) and an on/off ratio of similar to 10(9).

The development of thin-film transistors (TFTs) using 2D materials is crucial for enabling scalable, low-cost, and flexible electronics. Currently, 2D TFTs with the highest performance have been achieved by using ionic-liquid gating (ILG), a technique suited for proof-of-concept studies. However, ILG suffers from slow switching speeds, temperature sensitivity, poor long-term stability, and integration challenges, making it unsuitable for practical use. Moreover, typical fabrication methods for 2D TFTs involve harsh conditions such as strong acids or high temperatures (>300 °C), limiting integration with flexible substrates. This work provides the first demonstration of an ILG-free, all-2D-material TFT fabricated onto a flexible substrate. Water-based graphene and hexagonal boron nitride (h-BN) inks are printed to deposit the electrodes and dielectric layers, respectively. The MoS2 channel is produced via supramolecular interfacial self-assembly, yielding uniform, monolayer-rich films transferable to rigid and flexible substrates. The resulting TFTs operate below 3 V, exhibit negligible leakage current, and achieve field-effect mobilities up to 0.46 cm2 V-1 s-1 (rising to 2.47 cm2 V-1 s-1 with silver electrodes) measured under ambient conditions, while maintaining excellent mechanical flexibility. This work establishes a low-cost and scalable solution-processable platform for flexible electronics based on 2D materials that match requirements for practical applications.

The reliable integration of many electronic devices based on 2D materials is an open issue that faces the challenges related to the thickness inhomogeneity of the CVD grown material on large scale. We report on our experimental study of the correlation between the field-effect mobility of transistors based on semiconductive MoS2 and the material thickness inhomogeneity resulting from a standard chemical vapor deposition process. This opens a new perspective in different class of 2D materials based devices, where the monolayer thickness is a limitation to the device performance, such as catalytic cells and optoelectronic detectors.

2D material inks have the potential to strongly impact printed electronics, offering exciting opportunities for flexible and wearable devices. However, their electrical performance is often hindered by the resistive nature of inter‐nanosheet junctions within randomly assembled nanosheet networks, limiting their efficiency compared to individual nanosheets. Overcoming this challenge necessitates a comprehensive understanding of the conduction mechanisms governing charge transport in these networks. In this study, a water‐based graphene ink is prepared via liquid‐phase exfoliation (LPE), deposited onto Si/SiO₂ substrates through inkjet printing, and electrically characterized over a wide temperature range (80–400 K) following thermal annealing at different temperatures. To interpret the temperature‐dependent conductivity, a Random Resistor Network (RRN) model is employed that accounts for spatial and energetic variability among nodes. With this approach low and high temperature transport regimes are effectively studied, identifying inter‐flake and intra‐flake hopping mechanisms and providing valuable insights into the factors governing charge transport. Using Monte Carlo simulations, the RRN model delivers statistically robust predictions while capturing temperature‐dependent transitions and annealing effects, achieving excellent agreement with experimental observations.

The growing field of conformable and bio-integrated electronics is enabling the development of innovative applications such as wearable sensors, electronic skin, and implantable devices. This evolution requires advanced materials and fabrication strategies capable of delivering electrical functionality without compromising mechanical compliance. In particular, understanding the electrical behavior of the metal–insulator–semiconductor (MIS) structure is fundamental, as it forms the gate stack in conformable transistors. Therefore, a detailed MIS electrical assessment is essential for the design and integration of reliable, flexible field-effect platforms and wearable electronic systems. Here, we present conformable MIS capacitors based on few-layer MoS 2 , inkjet-printed pedot:pss electrodes, and ultrathin bilayer poly(vinyl formal) (PVF) dielectrics on polyimide substrates, and we report their electrical behavior through capacitance–voltage ( C–V ) profiling and equivalent circuit modeling. To our knowledge, this is the first characterization of such a hybrid MIS structure by C–V measurements, providing direct insight into the dielectric and semiconductor contributions and validating the suitability of this technology for conformable electronics. Our results show a stable and reproducible capacitance modulation of about one order of magnitude under bias voltage changes at low frequencies ( ∼ 100 Hz ), with reliable operation for frequencies up 10 kHz , and robust performance within the investigated bending-induced strain range.

We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet FET at the ultimate nanosheet thickness, using 2-D materials (2DMs). In particular, our numerical study specifically explores the potential of multilayer vertically stacked GAA MoS2 FETs, considering different geometries and device parameters (e.g., number of stacked nanosheets, spacer dimensions, doping, and so on) with the aim of providing guidelines for obtaining high-performance devices. Sources of nonideality that have been considered are the effects of contact resistance and line-edge roughness (LER), which significantly affect the overall performance of NSFETs. Finally, circuit performance has been benchmarked by calculating the energy per switching and worst case delay of a 32-bit full adder circuit.

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits.

Two dimensional magnetic materials are at the forefront of the next generation of spintronic devices. The possibility to interface them with other van der Waals materials such as transition metal dichalcogenides has opened new possibilities for the observation of new and exiting physical phenomena. Here, we present a proof-of-concept valleytronic device based on CrBr_3-encapsulated WSe_2 showing an unprecedented valley splitting of ∼ 100 meV under compressive strain of the WSe_2, able to be tuned by the relative magnetization of the encapsulating layers. Multiscale transport simulations performed on this device show a spin-valley current with a polarization higher than 80% than is maintained in a range of ∼ 0.3 V gate voltage in a field-effect transistor configuration. The impact of the stacking configuration on the valley splitting is also evaluated.

We explore through numerical simulations the possibility of exploiting 2-D materials (2DMs)-based field effect transistors (FETs) as read-out devices for quantum cascade (QC) detectors. For this purpose, a deep investigation of the device parameter space has been performed while considering different 2DMs as channel material, such as graphene and transition metal dichalcogenides (TMDs), considering both short- and long-channel devices. We find that while graphene offers the highest current density for a given impinging power, it shows higher OFF-currents as compared to other solutions based on TMDs, which, eventually, can represent a better choice for this particular application.

Two dimensional magnetic materials are at the forefront of the next generation of spintronic devices. The possibility to interface them with other van der Waals materials such as transition metal dichalcogenides has opened new possibilities for the observation of new and exiting physical phenomena. Here, we present a proof-of-concept valleytronic device based on CrBr$_3$-encapsulated WSe$_2$ showing an unprecedented valley splitting of $\sim 100$ meV under compressive strain of the WSe$_2$, able to be tuned by the relative magnetization of the encapsulating layers. Multiscale transport simulations performed on this device show a spin-valley current with a polarization higher than 80$\%$ than is maintained in a range of $\sim$ 0.3 V gate voltage in a field-effect transistor configuration. The impact of the stacking configuration on the valley splitting is also evaluated.

Two-dimensional magnetic materials are at the forefront of the next generation of spintronic devices. The possibility to interface them with other van der Waals materials such as transition metal dichalcogenides has opened new possibilities for the observation of new and existing physical phenomena. Here, we present a proofof-concept valleytronic device based on CrBr3-encapsulated WSe2 showing an unprecedented valley splitting of -100 meV under the compressive strain of the WSe2, able to be tuned by the relative magnetization of the encapsulating layers. Multiscale transport simulations performed on this device show a spin-valley current with a polarization higher than 80% than is maintained in a range of -0.3 V gate voltage in a field-effect transistor configuration. The impact of the stacking configuration on the valley splitting is also evaluated.

This work demonstrates the use of 2D materials (2DMs) as identification tags by exploiting their unique shape. Electrochemical exfoliation enables the production of large quantities of optically accessible 2DMs with diverse morphology and large lateral sizes up to 20 mu m. Image processing techniques are used to facilitate shape identification and matching within a dataset of 500 unique nanosheets. Rotational and translation invariant shape matching with no false positive matches between over 100 000 unique shape pairings is shown. The approach enables individual nanosheets to be deposited onto products, such as packaging of luxury goods, pharmaceuticals, banknotes, etc., as a unique seal of authenticity. Quick inspection of the nanoscale tag by optical microscopy allows the shape to be compared against the genuine dataset, enabling unique identification. The optical features of 2D materials, such as Raman and/or photoluminescence signals can be used as an additional chemical fingerprint, making the anticounterfeiting solution very robust. 2D nanotags with unique shape and chemical fingerprint can be produced from layered materials by electrochemical exfoliation. Manufacturers can tag products with a single nanotag and record and store its unique properties. Consumers can record the shape of their products nanotag by optical microscopy and check product authenticity by matching its shape with a genuine record.image

Adapting electronics to perfectly conform to nonplanar and rough surfaces, such as human skin, is a challenging task, which could open up new applications in fields of high economic and scientific interest, ranging from health to robotics, human-machine interface, and Internet of Things. The key to success lies in defining a technology that can lead to ultrathin devices, exploiting ultimately thin materials, with high mechanical flexibility and excellent electrical properties. Here, we report a hybrid approach for the development of high-performance, ultrathin and conformable electronic devices, based on the integration of semiconducting transition metal dichalcogenides, i.e., MoS2, with organic gate dielectric material, i.e., polyvinyl formal (PVF) combined with inkjet printed PEDOT:PSS electrodes. Through this novel approach, transistors and simple digital and analogue circuits are fabricated by a sequential stacking of ultrathin (nanometer) layers on a few micrometers thick polyimide substrate, which guarantees the high flexibility mandatory for the targeted applications.