As technology nodes advance, the need for higher sensitivity optical inspection to identify critical defects has become extremely important for technology development. However, more sensitive optical inspection can induce more nuisance and hence more SEM non-visual (SNV) defects during review sampling. High SNV in the defect Pareto hinders the ability to get a true picture of the actual distribution of defect types on a wafer, and defect-of-interest (DOI) types that are crucial for process diagnostics can be missed. The culprit of this problem is the method of review sampling. Traditional review sampling consists of two parts: binning and defect selection. Binning is defined as a set of rules and conditions determined by human experience and judgment to categorize different DOI types. Then, defects are selected from each bin and reviewed by SEM. Due to the nature of high SNV from optical inspection, the random selection of defects will end up with high SNV in the defect Pareto. A defect Pareto with high SNV provides little value to yield learning. Because SEM review plus classification is limited by time and economic budget, improving the ability to predict whether a defect is DOI or SNV before SEM review is valuable. This paper introduces a machine learning based method suitable for high volume manufacturing that can increase the probability of finding DOIs during review sampling by integrating all available data sources, such as historical defect attributes from optical inspection, context information of the inspection recipe, design hotspots and metrology measurements. In addition to review sampling, this paper also illustrates other applications based on machine learning defect prediction, such as virtual process window discovery, and predicted defect types for trend monitoring. A predictive analytics platform was employed to allow defect type prediction based upon multiple inputs.

In preparation for EUV lithography (EUVL) in high volume manufacturing, a preproduction ASML NXE: 3100 step-and-scan system was used to assess overlay performance under mix-and-match between EUV and ArF lithography, which will be critical for the successful insertion of EUV lithography into high volume 1x node production. Overlay sources of variation associated with EUV were investigated, including mask pattern-placement error (PPE), scan direction, and processing order. Furthermore, this study also looks into overlay control strategy development specifically for EUV/ArF mix-and-match lithography. Systematic and random overlay components will be discussed, as well as possible overlay modeling and control options.

Optical bright field wafer inspection followed by repeater analysis is used to find a maximum number of programmed and natural defects on a EUV patterned mask. Each aspect of the inspection methodology affecting the sensitivity of the wafer inspection is optimized individually. A special focus is given to the wafer stack. Simulation is used to predict the optimum stack properties and experimental verification is performed through exposures on the IMEC EUV Alpha Demo Tool. The final result is benchmarked against state-of-the-art patterned mask inspection and blank inspection to evaluate the capabilities and limitations of the optical wafer inspection. In addition, the locations obtained by each inspection technique (wafer and mask) were reviewed on wafer by means of a new automated methodology that is based on a tight stage accuracy of both inspection tool and review SEM.

As advanced lithographical techniques progressively reach denser pitches, pattern collapse becomes increasingly an issue owing to the capillary forces of the receding liquid present at the development and rinse. Process control and development require a reliable investigation method to be able to detect and quantify pattern collapse with the requirement of being non-invasive for resist structures while maintaining a high throughput. In this paper we present an inspection method based on an optical defectivity detection tool and specially designed lithographic structures to maximize the probability of pattern collapse. Collapse quantification and wafer signatures are presented along with extensive SEM review such as to validate the inspection method.

Reticle Pattern Placement Error (PPE) has been identified as one of the key challenges of Double-Patterning Lithography (DPL) as the overlay of the circuit patterns between two masks is a critical achievement for successful implementation of the process. According to the 2009 ITRS roadmap, double-patterning lithography is expected to extend 193nm immersion lithography to the 23nm node by 2016 and the corresponding PPE requirements is 1.9nm. PPE between the two masks comprising a DPL mask pair affects the resulting critical dimensions of the circuit pattern and the final device performance. In this paper, we study how the reticle PPE can be affected by the pellicle. The pellicle can induce a mechanical stress on the reticle such that the actual placement of the circuit patterns on wafer will be distorted after the lithography process. This distortion effect is known as Pellicle-Induced Distortion (PID). We conducted experiments by using different combinations of pellicle frames and frame adhesives on a DPL mask pair to study how reticle PPE can change with each combination. We used the KLA-Tencor LMS IPRO4 mask registration metrology tool to measure the PPE before and after the mount/un-mount of each experiment combination. The analysis is done using the KLA-Tencor DEVA software to quantify how the pellicle can affect the individual reticle PPE and also the relative errors between the DPL mask pair.

The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen. Many of these challenges are novel to the industry due to the relatively large size of the vias and new processes such as wafer back-grinding and carrier bonding. This paper summarizes the initial trial process monitoring that has been used during via-first TSV process development at IMEC. This process is designed for SiC (system in chip) applications, using Cu-filled vias measuring 5 um wide by 22 or 50 um deep. While there are a variety of metrology and inspection applications for TSV processing, the main topics covered here are via size measurement, post-grind wafer inspection, and carrier wafer bonding inspection.

predecessor, Surfscan SP1, using a 488nm laser for the existing lithography processes, the benchmarked typical resist defects are already well understood. With the shorter wavelength and a higher power laser, the SP2 not only achieves a significant improvement in the sensitivity for contamination defects but also resolves the easily overlooked process-induced “flow” type of defects in the resist stack.

The switch from dry to immersion lithography has important consequences regarding wafer defectivity. It has been shown that for successful and efficient defect reductions related to immersion lithography the capability to distinguish immersion/patterning related defects from stack related defects is very useful during process control. These stack related defects can be observed after careful partitioning of individual layer inspections and the analysis of this data through DSA in Klarity. The optimisation of the dark field inspection SP2 tool, central in this paper, shows that improved sensitivity at adequate signal to noise ratio can be obtained on the resist stacks by using the smaller wavelength as the UV-Iaser light present in the SP2. For bare Si and BARC oblique incidence illumination gives the best sensitivity and captures the most defects. However monitoring of the resist and stacks with resist requires normal incidence illumination since the nature of defects and film result in a higher scattering intensity using normal illumination. The use of an optical filter and a 10% laser power also contributed to establishing a lower and stable background signal for each inspection scan. As immersion tool development is improved and immersion specific defectivity is reduced, the proportion of the stack related defects will become a significant fraction of the overall target for further defect reduction. This includes point defects (embedded particles) or flow defects (streaks) identified and classified using SURFimage. Finally this information is to be used to identify the defect origin(s) for ultimate elimination of defects in the stacks.