Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

As the overlay performance and accuracy requirements become tighter, the impact of process parameters on the target signal becomes more significant. Traditionally, in order to choose the optimum overlay target, several candidates are placed in the kerf area. The candidate targets are tested under different process conditions, before the target to be used in mass production is selected. The varieties of targets are left on the mass production mask and although they will not be used for overlay measurements they still consume kerf real estate. To improve the efficiency of the process we are proposing the KTD (KLA-Tencor Target Designer). It is an easy to use system that enables the user to select the optimum target based on advanced signal simulation. Implementing the KTD in production is expected to save 30% of kerf real estate due to more efficient target design process as well as reduced engineering time. In this work we demonstrate the capability of the KTD to simulate the Archer signal in the context of advanced DRAM processes. For several stacks we are comparing simulated target signals with the Archer100 signals. We demonstrate the robustness feature in the KTD application that enables the user to test the target sensitivity to process changes. The results indicate the benefit of using KTD in the target optimization process.

The newly emerging lithographic technologies related to the 32nm node and below will require a step function in the overlay metrology performance, due to the dramatic shrinking of the error budgets. In this work, we present results of an emerging alternative technology for overlay metrology - Differential signal scatterometry overlay (SCOL (TM)). The technique is based on spectroscopic analysis of polarized light, reflected from a "grating-on-grating" target. Based on theoretical analysis and initial data, this technology, as well as broad band bright field overlay, is a candidate technology that will allow achieving the requirements of the 32nm node and beyond it. We investigate the capability of SCOL (TM) to control overlay in a production environment, on complex stacks and process, in the context of advanced DRAM and Flash technologies. We evaluate several metrology mark designs and the effect on the metrology performance, in view of the tight TMU requirements of the 32nm node. The results - achieved on the KLA-Tencor's Archer tool, equipped with both broad band bright field AIM (TM) and scatterometry SCOL (TM) sensors - indicate the capability of the SCOL (TM) technology to satisfy the advanced nodes requirements.

Semiconductor manufacturers expect 193nm immersion lithography, supplemented by double patterning techniques, to remain the dominant patterning technology through the 32nm technology node. In this work, we examine focus-exposure and overlay data that show potential challenges for qualification and control of immersion lithography in double patterning applications. Although careful characterization has enabled significant engineering advances in the past year or two, overlay remains a concern for double patterning. Higher-order models and more efficient sampling are required to reach sub-2.5nm targets for model residuals.

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss some interim solutions for control of double patterning lithography (DPL), as well as some spacer-etch alternatives. We conclude with focus-exposure data showing some potential challenges for pitch-splitting strategies implemented in the context of immersion lithography.