The Scale Invariant Feature Transform (SIFT) extracts relevant features from images and video frames. The extracted features are robust against luminance variations, geometrical transformations, and image resolution. Due to its performances, the SIFT algorithm is of great importance in fields such as object recognition, content retrieval from image databases, robotic navigation, and gesture recognition. Main drawback of the SIFT algorithm is the high computational complexity. This paper presents the development of a hardware filtering accelerator for the implementation of SIFT-based visual search. The accelerator works in the frequency domain, operating on a block-by-block basis. This enables to work faithfully to the original Scale-Space theory, which employes non-separable Laplacian of Gaussian (LoG) filters. The targeted throughput is of similar to 20 fps, making the coprocessor suitable for real time processing.

Multispectral and Hyperspectral Images are wide-spread in Remote Sensing and Space Imaging Applications: they are typically three dimensional arrays of images and their raw content may include thousands of bands for a total of over a billion pixels. For adequate storing and transmission over satellite communication links a proper compression scheme is required. In this paper a FPGA implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 standard algorithm is presented. The implementation results refer to a space-class device (Xilinx Virtex 5QV FX130T). The proposed architecture, composed by the Virtex5 FPGA and an external DRAM, implements circuital-oriented architectural improvements over the standard algorithm formulation. The proposed circuit, that is also user configurable in various aspects, overcomes the state of the art in terms of image pixel throughput (55.4 MSamples/s) and has a negligible footprint in terms of resource allocation (4%) for the selected FPGA.

Computer Vision is a more and more pervasive technology in nowadays image and video processing applications: examples include image driven search, stereoscopical matching, panorama stitching and industrial automation. Compact Descriptors for Visual Search (CDVS) is an algorithm for Computer Vision recently proposed as part of the MPEG-7 standard: it has the ability to select points of interest in the image (also referred to as keypoints) that exhibit robustness, in a certain degree, with respect to changes like homogeneous variations in luminance, changes in point of view, rotations, rescaling and geometrical distortion of the image. Keypoint Refinement is a phase of the CDVS algorithm which is aimed at discarding candidate keypoints that are likely to be unstable for their algebraic properties. This paper presents an FPGA circuit design that implements this phase on fixed point data with real time compatible throughput. Implementation results show a negligible impact on resources allocation even on mid-sized FPGAs.

In the present days of digital revolution, image and/or video processing has become a ubiquitous task: from mobile devices to special environments, the need for a real-time approach is everyday more and more evident. Whatever the reason, either for user experience in recreational or internet-based applications or for safety related timeliness in hard-real-time scenarios, the exploration of technologies and techniques which allow for this requirement to be satisfied is a crucial point. General purpose CPU or GPU software implementations of these applications are quite simple and widespread, but commonly do not allow high performance because of the high layering that separates high level languages and libraries, which enforce complicated procedures and algorithms, from the base architecture of the CPUs that offers only limited and basic (although rapidly executed) arithmetic operations. The most practised approach nowadays is based the use of Very-Large-Scale Integrated (VLSI) digital electronic circuits. Field Programmable Gate Arrays (FPGAs) are integrated digital circuits designed to be configured after manufacturing, on the field. They typically provide lower performance levels when compared to Application Specific Integrated Circuits (ASICs), but at a lower cost, especially when dealing with limited production volumes. Of course, on-the-field programmability itself (and re-programmability, in the vast majority of cases) is also a characteristic feature that makes FPGA more suitable for applications with changing specifications where an update of capabilities may be a desirable benefit. Moreover, the time needed to fulfill the design cycle for FPGA-based circuits (including of course testing and debug speed) is much reduced when compared to the design flow and time-to-market of ASICs. In this thesis work, we will see (Chapter 1) some common problems and strategies involved with the use of FPGAs and FPGA-based systems for Real Time Image Processing and Real Time Video Processing (in the following alsoindicated interchangeably with the acronym RTVP); we will then focus, in particular, two applications. Firstly, Chapter 2 will cover the implementation of a novel algorithm for Visual Search, known as CDVS, which has been recently standardised as part of the MPEG-7 standard. Visual search is an emerging field in mobile applications which is rapidly becoming ubiquitous. However, typically, algorithms for this kind of applications are connected with a high leverage computational power and complex elaborations: as a consequence, implementation efficiency is a crucial point, and this generally results in the need for custom designed hardware. Chapter 3 will cover the implementation of an algorithm for the compression of hyperspectral images which is bit-true compatible with the CCSDS-123.0 standard algorithm. Hyperspectral images are three dimensional matrices in which each 2D plane represents the image, as captured by the sensor, in a given spectral band: their size may range from several millions of pixels up to billions of pixels. Typical scenarios of use of hyperspectral images include airborne and satellite-borne remote sensing. As a consequence, major concerns are the limitedness of both processing power and communication links bandwidth: thus, a proper compression algorithm, as well as the efficiency of its implementation, is crucial. In both cases we will first of all examine the scope of the work with reference to current state-of-the-art. We will then see the proposed implementations in their main characteristics and, to conclude, we will consider the primary experimental results.

Compact Descriptors for Visual Search (CDVS) has been recently proposed as the part of the MPEG-7 standard which encompasses technologies and algorithms for the automatic retrieval of visual information from images and videos. A critical part of these algorithms is the selection of points of interest, also referred to as key points, within the given frame. The extracted features need to exhibit robustness against changes as luminance variations, geometrical transformations, and image rescaling. Such characteristics are typical of feature extraction techniques based on the Scale-Space theory and on the Laplacian-of Gaussian (LoG) kernels. In CDVS, a key point detection algorithm based on filtering with LoG kernels is proposed: being these filters non-separable, filtering in space domain requires the computation of 2D-convolutions, which in turn results in the algorithm being heavily demanding in terms of computational cost when performed in such a domain. As a consequence, we propose a frequency domain approach to CDVS key point extraction, which is at the core of the processor described in this paper. The main drawback connected to frequency domain operation is related to buffering: to reduce this, the proposed processor operates on a block-by-block basis while exploiting the characteristics of the CDVS algorithm to reduce buffering to a minimum. The architecture proposed herein, deployed on an ALTERA Stratix IV FPGA, is capable of extracting key points at a maximum frame rate over 20 fps, proving itself suitable for real-time applications.