Accurate vessel detection and timely information extraction from optical remote sensing imagery are essential for a wide range of maritime surveillance operations, both civilian and defense-related. These include vessel tracking, unauthorized fishing, illegal migration monitoring, and search and rescue missions. Although artificial intelligence (AI) is a key component for achieving reliable and accurate detection in satellite imagery, traditional AI-based remote sensing methodologies rely on ground-based image processing. This dependence leads to significant delays between data acquisition and the generation of actionable insights, which may hinder rapid decision-making during critical maritime situations such as sea disasters. To address this challenge, we propose a novel hardware design based on the Microchip PolarFire System-on-Chip for low-power, real-time vessel detection onboard spacecraft. Our design integrates the FPGA-based CoreVectorBlox engine to accelerate the inference process of SR-YOLOv5s-an enhanced object detection framework built upon YOLOv5s. This detector incorporates a single image super-resolution backbone that allows the extraction of fine details and features of small targets of interest, thus improving detection performance. Experimental results demonstrate that SR-YOLOv5s consistently outperforms the baseline YOLOv5s framework in vessel detection. The model provides high accuracy in detecting very small targets (area <= 7 x 7 pixels), achieving a mAP50 of 0.4658 compared to 0.2832-an absolute improvement of 18.26 percentage points. When deployed on the PolarFire FPGA, the end-to-end pipeline sustains real-time operation with an inference latency of 55 ms per frame and an average dynamic power consumption below 1.2 W. These results confirm the suitability of our approach for power-constrained onboard processing and demonstrate its effectiveness as a solution for low-latency alert generation in maritime surveillance through edge-based analysis of Earth observation imagery.

Inexact arithmetic units trade precision for improvements in energy efficiency, silicon area, and speed. Most existing designs focus on non-negative numbers and, when used in real applications, rely on Sign and Magnitude (SM) transformations to deal with signed values mitigating most of the advantages obtained in the first place. This work investigates circuits for the approximate negation of numbers in two’s complement (2’sC) format that offer a middle ground in terms of error and energy efficiency when compared to the exact 2’sC negation and the more aggressive one’s complement (1’sC) negation method, thus obtaining a general purpose tool for approximate computing that can be seamlessly integrated into existing designs. The paper demonstrates that by using this tool it is possible to exploit unsigned approximate arithmetic circuits in signed applications, achieving slightly lower error with no additional power compared to the commonly used 1’sC approximation, or significantly reduced error, while still lowering power dissipation relative to exact 2’sC negation. We derive analytical expressions for error characteristics and present a hardware implementation. The resulting versatile technique can be exploited to compute absolute values or to convert SM representations into 2’sC format.We incorporate the investigated circuits into several approximate architectures using a 14 nm FinFET standard cell library. The resulting designs, when compared with 1’sC negation, are able to improve accuracy (achieving up to 30% error reduction in approximate multipliers and 10dB PSNR gain in H.264 video compression) while still reducing the power dissipation.

In this paper, we present a novel accumulator architecture optimized for applications requiring a large number of guard bits, such as Cascaded Integrator-Comb (CIC) filters. Our approach leverages the disparity between the dynamic range of the input signal and the accumulator register by dividing the architecture into three sub-circuits: a high-speed LSB accumulator, a low-power increment evaluator, and a slow-speed MSB accumulator. This partitioning significantly reduces switching activity and clock frequency for MSB computation, resulting in improvements in power-delay-product and areadelay-product.

In this paper, we propose a novel low-power implementation of the radix-22 Fast Fourier Transform (FFT) processor that exploits optimized multiplications and low-voltage memory buffers. The FFT computation requires complex products between input samples and precomputed coefficients, known as twiddle factors, as well as a large number of memory elements to store intermediate signals. To reduce power consumption, we bypass multiplications when twiddle factors are equal to zero or one. Furthermore, we introduce a fixed-width technique that lowers multiplier complexity for non-trivial coefficients by pruning the least significant columns of the partial product matrix and discarding the most significant partial products with low activation probability. To further minimize power consumption, we lower the supply voltage of memory buffers, creating two power domains in the design. Post-synthesis analysis in 28 nm technology shows that the proposed FFT achieves superior SNR and MSE compared to existing implementations, with reductions of 33% in power consumption and 30% in the power-delay product. In an OFDM receiver, the design also achieves optimal bit error rate performance under various levels of channel noise.

Artificial Intelligence (AI)-driven autonomous on-board data processing is essential for future space missions, enabling timely decision-making in scenarios like planetary exploration, in-orbit servicing, and Earth Observation (EO). To overcome latency and reliance on ground control, AI models must run directly onboard. While edge AI and low-power accelerators have improved deep learning (DL) deployment on embedded systems, most commercial hardware lacks the radiation tolerance needed for deep-space missions. Space-qualified Field-Programmable Gate Arrays (FPGAs) offer a robust solution, combining energy efficiency, fault tolerance, and in-flight reconfigurability. This adaptability allows spacecraft to update AI models during missions without hardware changes. This paper reviews DL acceleration strategies for space applications, focusing on image processing, and presents a case study using the ANHEO platform, developed by TSD-Space and co-funded by the Italian Space Agency (ASI), demonstrating the benefits of FPGA reconfiguration in spaceborne AI systems.

In this paper, we propose a novel approximate multiplier with error-improved logarithmic and antilogarithmic conversion. In logarithmic multiplication, the forward and backward conversions to the logarithm domain introduce errors in the product. To recover accuracy, we apply an offset when logarithm and antilogarithm are computed, and find suitable values for these offsets in order to make the approximation error with zero mean. The hardware structure of the proposed multiplier is described for signed arithmetic, and a novel hardware-efficient approach, able to compute the sign of the output, is also proposed. Error metrics and synthesis analyses in a 28nm CMOS technology show that our multiplier offers the best accuracy-hardware performance for MRED<4x10(-2). Furthermore, remarkable results are achieved also in JPEG compression, exhibiting SSIM and PSNR metrics competitive with the state-of-the-art.

Approximate arithmetic circuits sacrifice computing accuracy in exchange for improvements in power, area, and speed. Many approximate binary multipliers that use 4-2 compressors have been proposed but most of the proposals have error performances that depend on the order in which the inputs are connected to the compressors. This complicates the design and prevents a fair comparison among different approximate multipliers. The paper proposes the input order invariant approximate 4-2 compressors, whose behavior remains consistent regardless of the order of input signals. We derive the complete set of such compressors and utilize them to synthesize 8-bit multipliers. Our analysis reveals that only a limited subset of input order invariant approximate 4-2 compressors offers an optimal balance between error and power savings. Furthermore, we demonstrate that this optimal set of 4-2 compressors can be strategically distributed within the columns of the multiplier to further enhance the trade-off between error and power efficiency. The proposed circuits, once implemented in a 14 nm FinFET standard cell technology, favorably compare against the state of the art.

In this paper, we present a novel low-power floating-point multiplier design that leverages dynamic segmentation to enhance efficiency. Our approach approximates the mantissa product through a simple addition of dynamically extracted input segments, supplemented by an additional correction term implemented through a small, hardwired lookup table. Compared to previous proposals, our FPM shows optimal results in terms of the power-accuracy trade-off, with power savings exceeding 85% compared to an exact implementation. The proposed multiplier offers remarkable performance in image processing applications, with Structural Similarity Index (SSIM) values approaching 1 and Peak Signal-to-Noise Ratio (PSNR) reaching up to 66dB.

In this paper we investigate a novel approximate multiply-and-accumulate (MAC) unit, that computes Y = A×B+C using static segmentation. The proposed architecture uses a unique carry-propagate adder and performs segmentation on the three operands A, B, and C, to reduce hardware cost. The circuit can be configured at design-time by two parameters. The first one controls the segmentation on A and B, while the second one controls the segmentation on C and the adder length. An error compensation technique is also employed, to reduce the approximation error. Error analysis and implementation results in 28nm CMOS for 8-bits multiplier with 20-bits and 24-bits addition are presented. The proposed approximate MACs outperform the state of the art, showing the largest power saving when the mean relative error distance (MRED) is larger than 2×10 −3 and 4×10 -5 for 20 and 24-bits addition, respectively. For MRED of about 6×10 −3 the proposed approximate MAC with 20-bits addition exhibits a power reduction larger than 60% compared to the exact MAC and larger than 27% compared to the state-of-the-art approximate MACs. Application examples to image filtering and template matching show that proposed approximate circuits are good candidates in applications where their error performances are acceptable.

Approximate computing is a technique that sacrifices the accuracy of the result for an advantage in terms of power, area, and speed. It is useful for error-tolerant applications such as image and video processing. Many approximate arithmetic circuits can be devised using approximate versions of the basic binary full adder that simply adds three bits to generate carry and sum. Therefore, the approximate full adder has been the subject of extensive investigation in recent years. In this paper we present a comprehensive analysis of approximate full adders, by synthesizing in a FinFET 14 nm technology the whole set of possible designs, achievable by modifying one or more entries of the full adder truth-table. Our exhaustive analysis shows that only a few out of the many thousands of synthesized circuits perform reasonably well as approximate full adders. Our analysis re-discovers the approximate full adders already proposed in the literature and identifies some new ones. Examples of using the newly discovered approximate full adders in typical error resilient applications are provided, showing the performance and the usefulness of approximate arithmetic circuit designs in the real-world.

In this paper we propose a novel approximatefloating-point divider based on bidimensional linear approx-imation. In our approach, the mantissa quotient is seen asa function of the two input mantissas of the divider. Thedomain of this two-variable function is partitioned intonxxn ysubregions, named tiles, wherenx,n yare chosen as powers oftwo. In each tile the quotient is approximated with a linearcombination of the input mantissas. To achieve fine accuracy,an optimization problem is formulated within each tile todetermine the optimal coefficients for the linear combination,which minimize the Mean Relative Error Distance (MRED) of thedivider. Furthermore, to make hardware implementation moreeffective, the minimization problem is appropriately modified tosearch for optimal quantized coefficients. The hardware structureof the divider only requires a small look-up table to storethe linear approximation coefficients, and a carry save addertree. The proposed architecture is highly tunable at design-timeover a wide range of accuracy, depending on the number oftiles chosen for the approximation. The obtained results demon-strate error performance and hardware features superior to thestate-of-the-art. The proposed dividers define the Pareto front,considering the trade-off between power-delay-product vs.MREDand area-delay-product vs.MRED, forMREDin the range of4x10(-3)-2x10(-2). Application results for JPEG compressionand tone mapping further highlight the strength of our proposal,which exhibits Structural Similarity Index (SSIM) very close to1 in all cases and Peak Signal-to-Noise Ratio (PSNR) up to 45 dB.

Floating-point division involves the computation of the ratio (1 + Mx)/(1 + My), where Mx and My represents the mantissas of the input values. In this paper, we propose a new method for approximating this operation using a linear function of Mx, with coefficients that depend on My. The coefficients are calculated to minimize the Mean Relative Error Distance (MRED) of the approximation. To this end, the range of My is partitioned in N sub-intervals where the minimization of MRED is formulated as a linear programming problem, whose solution gives optimal coefficient values. The hardware implementation requires a small lookup table, two multipliers and an adder. An aggressive coefficients quantization is exploited to further optimize the design. Obtained MRED improves by increasing N , ranging from 1.4% to 0.33%. Implementation results in a 28nm CMOS technology show that the proposed design outperforms the state-of-the-art, offering the best trade-off between hardware complexity and accuracy. Results for two image processing applications, change detection and JPEG compression, demonstrate remarkable performance, with SSIM very close to 1 and PSNR values exceeding 50dB.

In this paper, we analyze the performances of an Enhanced Static Segment Multiplier (ESSM) when the inputs have both uniform and non-uniform distribution. The enhanced segmentation divides the multiplicands into a lower, a middle, and an upper segment. While the middle segment is placed at the center of the inputs in other implementations, we seek the optimal position able to minimize the approximation error. To this aim, two design parameters are exploited: m, defining the size and the accuracy of the multiplier, and q, defining the position of the middle segment for further accuracy tuning. A hardware implementation is proposed for our generalized ESSM (gESSM), and an analytical model is described, able to find m and q which minimize the mean square approximation error. With uniform inputs, the error slightly improves by increasing q, whereas a large error decrease is observed by properly choosing q when the inputs are half-normal (with a NoEB up to 18.5 bits for a 16-bit multiplier). Implementation results in 28 nm CMOS technology are also satisfactory, with area and power reductions up to 71% and 83%. We report image and audio processing applications, showing that gESSM is a suitable candidate in applications with non-uniform inputs.

Approximate computing is a new approach that can help to reduce power consumption in error-resilient applications. Although many works have been proposed for fixed-point multipliers with predetermined levels of accuracy, they are not able to adapt to a wide range of applications, that need floating-point calculations with time-varying requirements. In this paper, we introduce an adjustable floating-point multiplier in which groups of partial products can be dynamically truncated, while the approximation error is reduced with the help of a simple rounding technique. In the proposed floating-point multiplier, precision and power can be adjusted at run-time based on the users' requirements. The developed circuits are synthesized in TSMC 28 nm CMOS technology. The comparison with the state-of-the-art shows a good trade-off between error and power consumption. Furthermore, we demonstrate the suitability and versatility of our multiplier through image processing applications, proving that it can be usefully employed in real-world scenarios.

Error resilient applications benefit from the use of approximate computing techniques that enhance electrical performances while allowing a deviation from the exact result. Many operations in signal processing require the square of a signal. Despite the fact that the squaring operation can be regarded as a special multiplication case, it is often preferable to develop independent squaring circuits to exploit possible architectural symmetries. This paper proposes novel approximate binary squarers, obtained by recursively exploiting 4-bit approximate multipliers and squarers. The final designs cover a wide range of computing precision, providing the user with multiple choices of different cost vs. accuracy trade-offs. The proposed circuits, as well as competitive designs, are synthesized targeting a 14 nm FinFET technology to determine the electrical characteristics. It is demonstrated that the proposed squarers outperform the state-of-the-art in terms of power vs. precision. Compared to the exact 8-bit squarer, the least dissipative proposed design reduces silicon area by 76%, power consumption by 71%, and critical delay by 72%. The same circuit dissipates 2.4% less power than the least dissipative design found in literature, while providing 34% more accurate results. The behavior of the considered designs is also tested in common error resilient applications, like signal demodulation and image processing.

Approximate computing, frequently used in error tolerant applications, aims to achieve higher circuit performances by allowing the possibility of inaccurate results, rather than guaranteeing a correct outcome. Many contributions target the binary multiplier aiming to minimize the complexity of this common yet power-hungry circuit. Approximate recursive multipliers are low-power designs that exploit approximate building blocks to scale up to their final size. In this paper, we present two novel 4×4 approximate multipliers obtained by carry manipulation. They are used to compose 8×8 designs with different error-performance trade-off. The final circuits exhibit a competitive behavior in terms of error while reducing the power dissipation when compared to state-of-the-art proposals. The proposed multipliers and state-of-the-art designs found in the literature, have been synthesized targeting a 14nm FinFET technology to determine the electrical characteristics. Compared with an exact 8×8 multiplier, the least dissipative design proposed in this paper reduces power consumption and silicon area by 46%, and minimum delay by 21%. It also consumes 14% less power than the least power-hungry recursive circuit found in the literature, while offering 81% higher accuracy. Ιmage processing applications and a convolutional neural network are shown to demonstrate the effectiveness of the proposed multipliers.

In this paper a novel low-power approximate floating-point multiplier is presented. Since the mantissa computation is responsible for the largest part of the power consumption, we apply a novel approximation technique to mantissa multiplication, based on static segmentation. In our approach, the inputs of the mantissa multiplier are properly segmented so that a small inner multiplier can be used to calculate the output, with beneficial impact on power and area. To further improve performance, we introduce a novel segmentation-and-truncation approach which allows us to eliminate the shifter normally present at the output of the segmented multiplier. In addition, a simple compensation term for reducing approximation error is employed. The accuracy of the circuit can be tailored at the design time, by acting on a single parameter. The proposed approximate floating-point multiplier is compared with the state-of-the-art, showing good performance in terms of both precision and hardware saving. For single-precision floating-point format, the obtained NMED is in the range 10−5–7 × 10−7, while MRED is in the range 3 × 10−3–1.7 × 10−4. Synthesis results in 28 nm CMOS show area and power saving of up to 82% and 85%, respectively, compared to the exact floating-point multiplier. Image processing applications confirm the expectations, with results very close to the exact case.

Approximate computing is a fast-emerging paradigm promising higher circuit performances in error tolerant applications. Binary multipliers are a common target for approximate computing due to their complexity and the multitude of their applications. In this paper, we investigate approximate recursive multipliers based on novel 4x4 multiplier blocks. We present three approximate 4x4 multipliers, with different error-precision trade-off, obtained by carry truncation and error compensation. These basic blocks are exploited to design 8x8 approximate multipliers. The proposed circuits are implemented in a 14 nm FinFET technology and show improved performance compared to the state-of-the-art.

In this paper, a novel implementation is proposed for the Delayed LMS (DLMS) filter, able to reduce the power dissipation while preserving regime performances. The approach relies on the observation that the error signal is small in magnitude and oscillates around zero when the circuit is close to the convergence point. Therefore, the most significant bits of the error signal continuously toggle from positive to negative values causing high switching activity in the multipliers of the feedback section. This paper proposes to employ a sign-modulus representation of the error signal, to substantially reduce the switching activity of the feedback path of the filter. Additional approximation techniques are also devised to further reduce power dissipation. Comparisons with the state-of-the-art show that the proposed filter is the only one able to approach the MSE of the exact implementation with a remarkable reduction of power dissipation. A test-chip in TSMC 28nm CMOS technology has been realized to experimentally verify the validity of our technique. The experimental results show the possibility of saving up to 45.4% of power consumption with respect to the exact implementation of the filter.