Among various methods for generating artificial tactile sensations, a haptic device that employs electrical stimulation has attracted significant attention due to its high potential for realizing hyper-realistic touch. Considering the high skin impedance and the dense population of tactile receptors in the fingers, achieving a high-resolution electrode design with high-power operation and a flexible form-factor is required. In this study, an electrical stimulation haptic device employing a high-power transistor with an active matrix (AM) design on a flexible substrate was demonstrated. We optimized parameters for the thin-film transistor (TFT) employing Indium-Gallium-Zinc-Oxide (IGZO) to sustain biphasic signal conditions as well as high power driving for electrical stimulation and its compatibility with low-process temperature for flexible form-factor. In order to secure the operating range of the driving TFT, the skin resistance value was measured based on the actual electrical stimulation waveform and confirmed to be 20-30 k Omega on average. The resulting device achieved a spatial resolution of 64 channels within a 1 cm(2) area. To achieve high drain current of TFT, a comb-shaped design of source and drain was suggested. The TFT can transfer high biphasic voltage (similar to +/- 50 V) with high simulation current (>10 mA). Therefore, the electrical stimulation device with high electrode density can supply sufficient power with wide bipolar stimulus signal swings stably for finger skin stimulation and various human interface devices.

A transistor with fully laminated plate-type triode electrodes, source, drain and gate offers higher current density than a typical transistor design by allowing a 2D current path. Nanoscale transistors face challenges like off-state leakage, so we introduce a new design using a laminated plate-type architecture and a dual-modulation strategy to improve performance and stability. Both top and bottom gates are used as active electrodes to fully control the channel's thickness. A micro-hole patterned electrode is employed to enable effective gate field penetration into the channel, while a graphene electrode facilitates Fermi-level modulation and improves field transfer. Furthermore, a leakage blocking layer is inserted to suppress unwanted carrier injection in the source and drain overlap regions. The device achieves low off-state current of ≈10-12 A and an on/off-current ratio exceeding 106 at VDS of 3 V. It also delivers high output currents under low-voltage operation (1 mA cm-2 at 0.1 V and 50 mA cm-2 at 1 V). Despite a nanoscale channel length, the device maintains near-zero VTH. The fully encapsulated channel shows strong reliability against bias stress and light. This work shows that a laminated vertical design with dual-gate control effectively enhances the stability of nanoscale transistors, highlighting their potential for next-generation low-power logic, memory, and flexible electronics.

Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 °C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 °C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric–channel interface, and structural interlayer) and how these steps jointly determine stack-relevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 °C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15–55 nm) and air-anneal duration (0–180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec−1) and the smallest combined bias-stress drift (|ΔVth| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the VO-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within ΔVth ≈ +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 °C pathway toward a polymer-ready monolithic ZnO TFT stack.

Electrical noses that mimic the human olfactory system have been developed to detect odors or flavors. Unfortunately, little research on sensing reactions to various odors like a human nose can be found in the literature. Herein, an electronic nose is proposed using a multi-thin film transistor (TFT) sensor array with various polymer selectors and multi-output signal processing to detect various odorants with high selectivity. Through the combination of multi-output produced by eight polymer variables based on indium gallium zinc oxide (IGZO) TFTs, a specific radar pattern and its selectivity are generated for the eight different odor substances. Eight multi-output signal processing reduced the correlation coefficient of similarity from 77.9% to 45% relative to the case of four multi-output processing. Because the polymers have different functional groups, polymers showed specific reactions to various odorants, like the human's system, and multi-output analysis could distinguish various odors, even if polymers did not show single selectivity to a specific odor. And the sensitivity improved when compared to two-terminal structures by using TFTs based on IGZO. The advantage is that it can classify multiple odors with good selectivity and sensitivity. This sensor and signal processing concept can be applied to E-nose systems capable of odor monitoring.

To enhance odor selectivity for electronic nose (E-nose) applications, a voltage modulation odor sensing approach based on polymer-based thin-film transistors (TFTs) is proposed. The sensor array was fabricated using eight non-conductive functional polymers (PAS, PC, PMMA, PS, PVA, PVB, PVCA, and SAA) as channel materials, and their responses to five representative odorants were measured under gate voltage sweeping conditions. The voltage-dependent response profiles were visualized using radar plots, and odor discrimination performance was quantitatively evaluated via normalized mean squared error (MSE) analysis. PAS and PVB exhibited average MSE values of 1.711 and 0.918 among the individual polymers. Notably, the combination of PAS and PVB resulted in a significantly higher MSE of 2.168, exceeding the value of 1.3954 observed for the full eight-polymer array and thus demonstrating superior odor selectivity. These results indicate that the synergistic effect of complementary polymer properties and gate bias modulation enables high-dimensional odor discrimination with reduced sensing elements. The gate bias control modulation can effectively simplify sensor architecture while maintaining high odor discrimination capability.

A transistor design employing all vertically stacked components has attracted considerable attention due to the simplicity of the fabrication process and the high conductivity easily realized by achieving nanolevel short channel lengths with two-dimensional current paths. However, fundamental issues, specifically the blocking of the gate electrical field to the semiconductive channel layer and high leakage current at the "off" state, have impeded this configuration in becoming a major transistor design. To address these issues, it has been proposed to introduce a blocking layer (BL) with embedded hole structures and source electrode with embedded hole structures, enhancing gate field penetration and carrier modulation. The hole structure embedded in the source and the BL on the drain induced a desirable combined effect of gate field penetration and carrier pathway modulation. The align accuracy and the hole size difference between BL and source electrode were confirmed as the most important design parameters for high performance of a transistor. We therefore proposed a self-aligning lithography method using a built-in mask that allows high alignment accuracy between the source hole structure and the BL hole structure on the drain over a large area without a high-resolution process system. This method also enables easy and fast fabrication of nanoscale channels with high performance. This design resulted in a transistor with an output of 28 mA/cm2 and an on-off ratio exceeding 106 at 1 mV of VDS. However, at 3 V of VDS, the off-current increased significantly due to short-channel effects in the all metal electrode design. To solve this issue, Fermi level-tunable graphene replaced metal electrodes, maintaining an off-current below 10 pA and an on-off ratio around 107 at 3 V. In addition, the device demonstrates robust electrical properties to light without any special treatment and is stable with a threshold voltage shift of less than 1 V under bias stress. This study demonstrates that the proposed vertical transistor design is a viable candidate as a new major transistor design for various applications.

AbstractFerroelectric field‐effect transistors (FeFETs) are increasingly important for in‐memory computing and monolithic 3D (M3D) integration in system‐on‐chip (SoC) applications. However, the high‐temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia‐based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle > 106, retention > 106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7 V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µC cm−2) and pattern recognition rate‐based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin‐film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

To realize a brain-machine interface, a neural probe is one of key hardware. For the neural probe, a high spatial resolution of an electrode array, high electrical sensitivity, and mechanical flexibility remain challenging and essential issues. In regard to these, implantable multi-electrode neural probe employing active-matrix design with field effect transistors (FETs) can attract attention due to their advantages of a suitable integration density and good signal-amplifying abilities. Therefore, we developed a flexible multi-electrode neural probe employing an active-matrix design based on a two-transistor (2T) scheme for application to a flexible neural signal recording probe. As a proof of concept, 4 ×8 electrode array (32 channels) with TFTs was demonstrated. For the flexible active-matrix design, back-gate indium-gallium-zinc-oxide (IGZO) thin film transistors (TFTs) was fabricated on a polyimide (PI). The TFTs used here can amplify signals and achieve a switching function to drive the active matrix. The probe structure was encapsulated by the same PI material again to achieve flexibility with good reliability, as the sandwich-like structure can induce a neutral plane on the TFT and electrodes. To ensure a high signal-to-noise ratio, the structural and process parameters of the TFT were studied. Among different annealing times and temperatures of the IGZO TFT, the optimized annealing condition of the TFT was found to be 250℃ a 1hour on a flexible substrate. The width over length of the transistors was optimized to 50 μm / 10 μm, and the field-effect mobility was 8.33 cm2/V·s. The on current was 2.28 ×10-6A at a low driving voltage of 5V. The transconductance was 2.16 μS and the threshold voltage (Vth) was 1.6V. By applying 5V, the switching TFT was turned on, and a doubly amplified signal (> 2.4 times) could be measured on the drain line. The electrode array probe with the active-matrix design can use for accurate neural recording and herald a new generation of flexible neural probes with high spatial resolutions.

Electrical noses that mimic the human olfactory system have been developed to detect odors or flavors. Unfortunately, little research on sensing reactions to various odors like a human nose can be found in the literature. We proposed an electronic nose using a multi‐thin film transistor (TFT) sensor array with various polymer selectors and multi‐output signal processing to detect various odorants with high selectivity. Through the combination of multi‐output produced by eight polymer variables based on IGZO TFTs, a specific radar pattern and its selectivity were generated for the eight different odor substances. Eight multi‐output signal processing reduced the correlation coefficient of similarity from 77.9% to 45% relative to the case of four multi‐output processing. Because the polymers have different functional groups, polymers showed specific reactions to various odorants, like the human’s system, and multi‐output analysis could distinguish various odors, even if polymers did not show single selectivity to a specific odor. And we improved the sensitivity compared to two‐terminal structures by using TFTs based on IGZO. The advantage is that it can classify multiple odors with good selectivity and sensitivity. This sensor and signal processing concept can be applied to E‐nose systems capable of odor monitoring.

To improve performances of nonvolatile charge trap flash memory devices, we propose an in situ Hf0.5Zr0.5O2 (HZO)/HfO2/Al2O3 stacked structure, which is compatible for Si with the metal–oxide–semiconductor (MOS) process based on all atomic layer deposition. Since the appropriate bandgap difference between Al2O3 and HfO2, stable charge trap operation is achieved. High-quality ferroelectric HZO film characteristics were showed by minimizing defects and Si diffusion through the sub-layer of Al2O3/HfO2. Therefore, HZO as a blocking layer enhances the memory performance of the charge trap structure due to its specific polarization effect. The proposed device has the high polarization characteristics of HZO (2Pr > 20 μ C/cm2) along with a MOS-cap window (>4 V), good retention capability (>10 years), fast program/erase response operation times (<200 μs), and strong durability (>105 cycles) while operating as a form of single level cell. By comparing Al2O3 and ferroelectric HZO as a blocking layer of the charge trap device, we confirmed that the HZO/HfO2/Al2O3 multi-layer structure had excellent characteristics according to various memory performance indicators. Our proposed high-performance charge trap flash memory can be employed in various applications, including Si-based three-dimensional structures with artificial intelligence systems.

Abstract The vertical thin film transistor (VTFT) has several advantages over the planar thin film transistor, such as a high current density and low operating voltage, because of the structural specificity. However, it is difficult to realize transistor operation in a VTFT because of the structural limitation that the gate field is blocked. As a solution, the conductivity modulation of a graphene electrode is studied with a micro‐hole structure as a gate field transfer electrode. The micro‐hole array pattern in the graphene allows better penetration of the gate field to junction and the work function to be modulated. Moreover, the patterning induces a doping effect on the graphene which results in a high barrier at the p–n junction and improves the conductivity in the device operation. The optimum performance is shown at 5 µm hole size and 30% hole ratio by analyzing the hole size and the area ratio. The proposed structure shows about 20 times higher on‐current than a planar transistor with a same active area. Compared to a VTFT using simple graphene working function modulation, the proposed structure has an on‐state current that is ten times higher and off‐state current that is reduced 50%, and therefore has an improved on–off ratio.

To fundamentally solve the bottleneck of Von Neumann’s computing architecture, a neuromorphic thin-film transistor (NTFT) employing Pb(Zr, Ti)O3 (PZT) was investigated. The indium gallium zinc oxide (IGZO) channel back gate TFT structure was chosen to solve the diffusion of atoms that form a channel layer during the annealing process for crystallization of PZT. A post-deposition process with IGZO after annealing PZT and using an oxide-based material as a channel structure can minimize the diffusion phenomenon of junction materials and oxygen together, which leads to a high and reliable performance of the NTFT. The basic operations of synapses short-term memory (STM) and long-term memory (LTM) were also analyzed to confirm the application of a neuromorphic device. The high dielectric constant and polarization properties of Pb(Zr, Ti)O3 (PZT) allow the power consumption of spike signals used in spike dependent plasticity change to be reduced to 10 pJ. Moreover, a wide dynamic range of Gmax / Gmin ≅ 1000 was obtained, and the channel conductance was maintained over 40000 seconds. The optimized pulse achieved multi-level states (>32), which made the learning process efficient. This study verified that the PZT-TFT structure has a high potential and merits for neuromorphic devices.

High selectivity of the sensor is one of the most important parameters for the electronic nose (E-nose) or gas sensor. However, many sensors have shown poor selectivity, even though some had high sensitivity. To solve this issue, we suggested a multi-sensor array concept, which consisted of thin-film transistors (TFTs) with various polymer selectors. By using TFT as a base sensor structure, sensitivity was significantly enhanced, and by adopting a polymer as the second dielectric layer, there was a remarkable improvement in selectivity. Some polymers showed unique selectivity to a specific odorant, whereas others had a moderate reaction to various odorants. Instead of common one-to-one matching between a sensor and an odorant, we used multi-output analysis using a dimensional bar chart. Eight different polymers TFTs made a specific chart pattern for four different odorants. Therefore, this sensor array and signal process concept can apply to the e-nose system, which can classify many odorants like a human simulator.

A thin-film transistor (TFT) with a color filter function achieved by designing periodic nanohole arrays in the metal electrodes was studied. Since this metal electrode is not opaque but transparent to a specific color of light, the TFT structure has unique optical characteristics that can be used in broader applications. An aluminum metal electrode with nanohole arrays permitted specific color transmission by the surface plasmon phenomenon, depending on the spacing between holes, from blue to red. Although the gate electrode of the TFT had a nanohole structure, its electrical characteristics and the electrical field distribution in the gate oxide were almost similar to that of a common metal electrode structure. The TFTs with the nanohole arrays showed similar electrical performances to general TFTs without the nanohole structure. The values of 0.7 V/decade subthreshold swing and >10(7) ION/IOFF ratio were measured. The TFTs with the nanohole arrays on the metal layer were transparent in a specific color range and still kept its original electrical functionality. Therefore, the color TFT structure can be a good solution for various applications such as a solution for the low aperture issue in organic light-emitting diode (OLED) displays or low reliability in a flexible transparent display while offering a simpler fabrication process.

The implications of graphene for tunneling diodes have attracted great attention due to the excellent electrical properties of graphene. Most graphene-based tunneling diodes have been fabricated with a vertical structure. They are limited by a complicated fabrication process. Herein, we present a lateral-structured graphene tunneling diode with asymmetric geometry. The asymmetric geometry induces strong electric field enhancement leading electronic band bending. Therefore, the asymmetry of the graphene tunneling is improved as much as 2.5 times. The lateral device structure opens up possibilities to apply graphene tunneling diodes in future electronic circuits.