Among various methods for generating artificial tactile sensations, a haptic device that employs electrical stimulation has attracted significant attention due to its high potential for realizing hyper-realistic touch. Considering the high skin impedance and the dense population of tactile receptors in the fingers, achieving a high-resolution electrode design with high-power operation and a flexible form-factor is required. In this study, an electrical stimulation haptic device employing a high-power transistor with an active matrix (AM) design on a flexible substrate was demonstrated. We optimized parameters for the thin-film transistor (TFT) employing Indium-Gallium-Zinc-Oxide (IGZO) to sustain biphasic signal conditions as well as high power driving for electrical stimulation and its compatibility with low-process temperature for flexible form-factor. In order to secure the operating range of the driving TFT, the skin resistance value was measured based on the actual electrical stimulation waveform and confirmed to be 20-30 k Omega on average. The resulting device achieved a spatial resolution of 64 channels within a 1 cm(2) area. To achieve high drain current of TFT, a comb-shaped design of source and drain was suggested. The TFT can transfer high biphasic voltage (similar to +/- 50 V) with high simulation current (>10 mA). Therefore, the electrical stimulation device with high electrode density can supply sufficient power with wide bipolar stimulus signal swings stably for finger skin stimulation and various human interface devices.

Recent advances in robotic systems have enabled ultrafine control and precision comparable to that of human hands. However, structural constraints of robotic hands require tactile sensors with high functional complexity and precision while maintaining a simple design. Analogous to vision sensors, tactile sensors would benefit from the ability to record key tactile parameters, including pressure, temperature, and surface texture. This study presents a multifunctional tactile sensor integrating a piezoelectric pressure sensor and a resistive temperature sensor within a single body, along with a tactile recorder system for real-time data acquisition and analysis. The temperature sensor’s electrodes also serve as those of the pressure sensor, achieving structural integration but functional separation. The sensor exhibits a response time of less than 10 ms and sensitivities of 0.69 mV/kPa and 2.7 Ω/℃ for pressure and temperature, respectively. A deviation of 4.68 mV across 25 sensing cells demonstrates excellent uniformity, enabling high-resolution surface mapping and 3D topography rendering. An experimentally derived compensation formula minimizes pyroelectric-induced errors, ensuring accurate pressure readout under varying temperatures. The tactile recorder visualizes and stores signals for subsequent analysis of surface texture and temperature-dependent tactile responses. This work demonstrates a structurally simple yet functionally rich platform for tactile sensing and recording in artificial tactile interfaces.

The development of high-performance optoelectronic devices based on 2D materials has attracted significant attention. However, conventional vertical stacking methods are limited by complex processes and interfacial defects. To overcome these challenges, we propose a simple and efficient one-step process to form an in-plane homojunction within a single n-type tin disulfide (SnS2) flake via direct laser irradiation. The core process, oxidative thinning, utilizes a focused 532 nm laser to locally convert a portion of SnS2 into tin oxide (SnOx). Consequently, an energy barrier arising from a work-function difference of approximately 0.7 eV is formed at the interface, promoting the separation of photogenerated electron-hole pairs. The fabricated photodetector demonstrates a fast response time (tau r/tau f = 474/299 ms), an improvement of several tens of times compared with the pristine SnS2 device. Furthermore, it exhibits a high responsivity (R) of 703 mA W-1, an external quantum efficiency (EQE) of 170%, and a remarkable specific detectivity (D*) of 2.35 x 1014 Jones, along with excellent operational stability. This laser-induced local conversion technique presented can provide a powerful and practical platform for developing next-generation flexible and wearable optoelectronic devices.

ABSTRACT Wide‐bandgap amorphous oxide semiconductors (AOSs), particularly indium‐gallium‐zinc‐oxide (IGZO), offer ultralow off‐current and back‐end‐of‐line compatibility, making them attractive for advanced dynamic random access memory (DRAM). In capacitor‐less two‐transistor (2T0C) DRAM, dual‐gate (DG) a‐IGZO TFTs are promising read transistors, but achieving a stable positive threshold voltage (V th ) typically reduces field‐effect mobility (µ FE ) and increases contact resistance (R C ), limiting fast operation. This study introduces a spatially selective laser annealing strategy that overcomes this limitation in a single step. The steep thermal gradient promotes oxygen incorporation at the top‐gate dielectric/channel interface, passivating defects without severely depleting carrier density. Simultaneously, WO x interlayer removal combined with oxygen redistribution forms conductive n + regions at source/drain contacts. This dual modification stabilizes the channel and reduces R C , enabling both high µ FE (37.9 cm 2 V −1 s −1 ) and a stable positive V th (0.27 V). The optimized devices exhibit small ΔV th under bias stress and reliable operation, demonstrating the read function of 2T0C DRAM, maintaining stable “0/1” state discrimination and wide memory windows (>10 5 ) for over 10 000 s. This single‐step process provides a practical route to overcome the performance‐stability trade‐off in AOS TFTs, highlighting strong potential for emerging memory applications.

“History repeats itself” is one of the well-known idioms, suggesting that patterns of events tend to recur over time and often lead to similar outcomes. By observing and learning from past patterns, valuable insights into the present and future can be gained. This recurring pattern is not limited to human society but is also evident in the evolution of technology. History is often described as a linear sequence of progress in which older technologies are replaced and left behind. Yet, time and again, innovation frequently follows a different trajectory: Ideas once considered obsolete can reemerge in unexpected and transformative ways. The vacuum tube is a compelling example of such technological recurrence.

Nanoparticle (NP)-based physical unclonable functions (PUFs) have attracted attention as a digital fingerprint technology that alternates with microfabrication-based PUFs by utilizing natural randomness at the nanoscale. Mostly NP-based optical PUFs have been proposed due to the absence of nanomaterial fabrication method compatible with microelectronics, but the need for a bulky optical readout system makes it difficult to utilize them in microelectronics. In this work, we developed the NP-based capacitor PUF (CAP-PUF) technology that can be read electrically and integrated into microelectronics while utilizing the benefit of the natural physical randomness of NPs. We incorporated a high-k BaTiO3 NP inkjet printing micropatterning process for the fabrication of the NP-embedded CAP-PUF array. The inkjet-printing parameters have been optimized to maximize the natural randomness of the BaTiO3 NP micropatterns by increasing the intrinsic stochasticity, especially the fluid dynamics that occurring during the multilayer printing. The BaTiO3 NP-embedded CAP-PUF array shows high security performance, showing the inter-hamming distance of 0.52, uniformity of 0.44, entropy of 0.989, and intra-hamming distance up to 0.064. High-k NP inkjet-printing-based CAP-PUFs can provide highly unique digital fingerprints based on the intrinsic randomness in nanoscale for microelectronics.

A transistor with fully laminated plate-type triode electrodes, source, drain and gate offers higher current density than a typical transistor design by allowing a 2D current path. Nanoscale transistors face challenges like off-state leakage, so we introduce a new design using a laminated plate-type architecture and a dual-modulation strategy to improve performance and stability. Both top and bottom gates are used as active electrodes to fully control the channel's thickness. A micro-hole patterned electrode is employed to enable effective gate field penetration into the channel, while a graphene electrode facilitates Fermi-level modulation and improves field transfer. Furthermore, a leakage blocking layer is inserted to suppress unwanted carrier injection in the source and drain overlap regions. The device achieves low off-state current of ≈10-12 A and an on/off-current ratio exceeding 106 at VDS of 3 V. It also delivers high output currents under low-voltage operation (1 mA cm-2 at 0.1 V and 50 mA cm-2 at 1 V). Despite a nanoscale channel length, the device maintains near-zero VTH. The fully encapsulated channel shows strong reliability against bias stress and light. This work shows that a laminated vertical design with dual-gate control effectively enhances the stability of nanoscale transistors, highlighting their potential for next-generation low-power logic, memory, and flexible electronics.

Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 °C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 °C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric–channel interface, and structural interlayer) and how these steps jointly determine stack-relevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 °C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15–55 nm) and air-anneal duration (0–180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec−1) and the smallest combined bias-stress drift (|ΔVth| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the VO-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within ΔVth ≈ +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 °C pathway toward a polymer-ready monolithic ZnO TFT stack.

The implementation of high-voltage (HV) applications in monolithic integration has led to increased demand for wide-bandgap high-voltage thin-film transistors (HVTFTs) to solve voltage mismatch problems between HV devices and complementary metal oxide semiconductor (CMOS) integrated circuits. However, typical HVTFTs possess several limitations, including low driving current due to the drain offset structure and high process temperature (>300 degrees C), limiting high-frequency switching operation and flexible substrate compatibility, thus impeding their application in flexible and wearable HV electronics. This study presents heterojunction wide-bandgap channel-based HVTFTs fabricated using amorphous indium tin zinc oxide (a-ITZO) and indium gallium zinc oxide (a-IGZO) to overcome the limitations of the current HVTFTs. Owing to the heterojunction channel layer, we achieved a much higher driving current of >0.37 mA/mm (I-D/W) at V-GS = 210 V and V-DS = 5 V with a flexible-electronics-compatible channel layer annealing temperature (150 degrees C), indicating that the TFTs can be even applied in HV flexible/wearable electronics. Therefore, ITZO/IGZO TFTs can withstand considerably higher power than single-layer IGZO HVTFTs, while exhibiting similar HV breakdown characteristics. Additionally, the ITZO/IGZO HVTFTs demonstrate superior electrical stability under high-voltage-bias conditions compared to conventional IGZO HVTFTs. Thus, heterojunction amorphous metal oxide TFTs are suitable for fast switching flexible HV electronic systems while gate-controlled by CMOS technologies.

Electrical noses that mimic the human olfactory system have been developed to detect odors or flavors. Unfortunately, little research on sensing reactions to various odors like a human nose can be found in the literature. Herein, an electronic nose is proposed using a multi-thin film transistor (TFT) sensor array with various polymer selectors and multi-output signal processing to detect various odorants with high selectivity. Through the combination of multi-output produced by eight polymer variables based on indium gallium zinc oxide (IGZO) TFTs, a specific radar pattern and its selectivity are generated for the eight different odor substances. Eight multi-output signal processing reduced the correlation coefficient of similarity from 77.9% to 45% relative to the case of four multi-output processing. Because the polymers have different functional groups, polymers showed specific reactions to various odorants, like the human's system, and multi-output analysis could distinguish various odors, even if polymers did not show single selectivity to a specific odor. And the sensitivity improved when compared to two-terminal structures by using TFTs based on IGZO. The advantage is that it can classify multiple odors with good selectivity and sensitivity. This sensor and signal processing concept can be applied to E-nose systems capable of odor monitoring.

Emulating and enhancing human olfactory capabilities, artificial olfactory technology provides adept detection of subtle odors, gases, and various chemical substances. Metal oxide semiconductors (MOSs) are ideal materials for next-generation artificial olfactory devices due to their outstanding gas sensing performance, characterized high sensitivity, high response speed, and robust stability, as well as their compatibility with microfabrication. For broader applications, developing a comprehensive database of diverse odorants is crucial, which necessitates expanding the types of MOS channels in artificial olfactory devices. This paper reports a laser-induced oxidation-based artificial olfactory device using a 7 × 3 sensor array composed of three metal oxides (SnO2-x, ZnOx, and WO3-x). By analyzing the response pattern of various odorants using a deep neural network, the device achieved 95.2% accuracy in classifying eight single odor molecules. Additionally, it successfully deconvoluted the types and concentrations of two odor mixtures and classified ten types of wine with accuracies of 91.3% and 92.5%, respectively. Furthermore, this study identified the proper number and arrangement of sensors for next-generation e-nose development. Our innovative artificial olfactory system can be integrated into various fields, such as the aromatic industry and virtual reality, making it a beneficial technology for future artificial olfaction applications.

Transparent electro-optical neural interfacing technologies offer simultaneous high-spatial-resolution microscopic imaging, and high-temporal-resolution electrical recording and stimulation. However, fabricating transparent, flexible, and mechanically robust neural electrodes with high electrochemical performance remains challenging. In this study, we fabricated transparent (72.7% at 570 nm), mechanically robust (0.05% resistance change after 50k bending cycles) ultrathin Au microelectrodes for micro-electrocorticography (µECoG) using a hexadentate metal-polymer ligand bonding with an EDTA/PSS seed layer. These transparent µECoG arrays, fabricated with biocompatible gold, exhibit excellent electrochemical properties (0.73 Ω·cm2) for neural recording and stimulation with long-term stability. We recorded brain surface waves in vivo, maintaining a low baseline noise and a high signal-to-noise ratio during acute and two-week recordings. In addition, we successfully performed optogenetic modulation without light-induced artifacts at 7.32 mW/mm2 laser power density. This approach shows great potential for scalable, implantable neural electrodes and wearable optoelectronic devices in digital healthcare systems.

The digitization of human senses has driven innovation across various technologies and transformed our daily lives, yet the digitization of olfaction remains a challenging frontier. Artificial olfactory systems, or electronic noses (e-noses), offer great potential for environmental monitoring, food safety, healthcare, and the fragrance industry. However, integrating sensor arrays that mimic olfactory receptors remains difficult, typically requiring complex, repetitive, and costly fabrication processes. In this research, we report the development of a porous laser-induced graphene (LIG) sensor array with in situ-doped cerium oxide nanoparticles for the classification of odorant molecules. By adjusting the laser irradiation parameters, we achieve a high degree of physical and chemical diversity in both LIG and CeOx. Consequently, a sensor array exhibiting diverse response patterns to different odorant molecules can be fabricated through one-step laser irradiation of a polymer precursor. Using t-distributed stochastic neighbor embedding (t-SNE) and support vector machine (SVM)-based machine learning, we accurately predict the type and concentration of nine odorant molecules used in perfumes and cosmetics, achieving a high accuracy exceeding 95%. This study provides a rapid and straightforward solution for creating functional olfactory receptor-mimicking arrays, advancing the development of artificial olfaction systems.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe2) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W1-xCrxSe2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe2, while CrxSey exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe2/W1-xCrxSe2/Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W1-xCrxSe2 alloy interface contact WSe2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 × 108 across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe2) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W1-xCrxSe2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe2, while CrxSey exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe2/W1-xCrxSe2/Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W1-xCrxSe2 alloy interface contact WSe2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 × 108 across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies.

The lack of p‐type conductivity in metal oxide semiconductors presents the major limitation for their integration into complementary metal‐oxide‐semiconductor (CMOS) technology, which requires both n‐type and p‐type semiconductors for balanced and efficient operation. Titanium dioxide (TiO 2 ) is known for its wide‐gap n‐type semiconductor characteristics, but it is challenging to convert it into a p‐type semiconductor. This study focuses on the semiconducting type conversion of TiO 2 via laser‐assisted oxidation and doping integration, enabling simultaneous Ti oxidation to form TiO 2 and type‐conversion‐friendly Al doping in a single step. When the laser power exceeds a specific threshold, Al cations from the underlying Al₂O₃ layer diffuse into the TiO₂ lattice. This selective incorporation of Al converts the intrinsic n‐type conductivity of TiO₂ to p‐type by substituting Ti⁴⁺ with Al 3 ⁺. The formation of TiO 2 and the incorporation of Al dopants are confirmed using X‐ray Photoelectron Spectroscopy and Energy Dispersive Spectroscopy Transmission Electron Microscopy. In addition, the fabrication of laser‐oxidized Al‐doped TiO 2 thin‐film transistors confirms that Al doping improves hole current and photostability. The laser‐induced Al‐doped TiO 2 offers an easy, simple, efficient, and controllable fabrication method for CMOS technology and advanced electronic devices.

Photothermal neuromodulation is a promising non-electrical neural stimulation technology for treating brain diseases through optically induced cell membrane temperature changes. However, the technology faces limitations in understanding its mechanism and impact on cellular behavior due to the restriction of directly measuring temperature changes at the cell interface from a very close distance during optical stimulation of neural cells, necessitating advancements in high-precision temperature sensing and electrical recording without light interference. This challenge is addressed by developing ultrasensitive cell membrane interface temperature sensors integrated with low-noise electrical recording capabilities. Transparent resistive temperature detectors, composed of a 10 nm thickness of ultrathin Au film fabricated by polyelectrolyte seed layer-induced thermal evaporation, achieved precise measurement and control of temperature changes without significant light interference and self-heating. A transparent electrode composed of the same ultrathin Au layer shows low-noise electrical recordings of neural signals upon photothermal stimulation. Using this multifunctional system, it is demonstrated that an average increase of 2.34 °C at neuronal cell surfaces results in over 95% suppression of hippocampal neural spike activities. The approach provides unprecedented insights into the mechanisms of photothermal neuromodulation and its effects on cellular behavior, paving the way for advanced treatments of neurological disorders.

A transistor design employing all vertically stacked components has attracted considerable attention due to the simplicity of the fabrication process and the high conductivity easily realized by achieving nanolevel short channel lengths with two-dimensional current paths. However, fundamental issues, specifically the blocking of the gate electrical field to the semiconductive channel layer and high leakage current at the "off" state, have impeded this configuration in becoming a major transistor design. To address these issues, it has been proposed to introduce a blocking layer (BL) with embedded hole structures and source electrode with embedded hole structures, enhancing gate field penetration and carrier modulation. The hole structure embedded in the source and the BL on the drain induced a desirable combined effect of gate field penetration and carrier pathway modulation. The align accuracy and the hole size difference between BL and source electrode were confirmed as the most important design parameters for high performance of a transistor. We therefore proposed a self-aligning lithography method using a built-in mask that allows high alignment accuracy between the source hole structure and the BL hole structure on the drain over a large area without a high-resolution process system. This method also enables easy and fast fabrication of nanoscale channels with high performance. This design resulted in a transistor with an output of 28 mA/cm2 and an on-off ratio exceeding 106 at 1 mV of VDS. However, at 3 V of VDS, the off-current increased significantly due to short-channel effects in the all metal electrode design. To solve this issue, Fermi level-tunable graphene replaced metal electrodes, maintaining an off-current below 10 pA and an on-off ratio around 107 at 3 V. In addition, the device demonstrates robust electrical properties to light without any special treatment and is stable with a threshold voltage shift of less than 1 V under bias stress. This study demonstrates that the proposed vertical transistor design is a viable candidate as a new major transistor design for various applications.