Affinity based electrochemical biosensing systems with integrated miniaturised interfaces has enabled key advancement toward rapid, sensitive, precise and deployable detection platforms. Manufacturing silicon micro/nano devices for biology interface has been a highly promising platform to design and develop electrochemical sensors for the detection of very low concentrations of the target molecules. However, the biofouling challenge of the biosensors when the surface is exposed to a complex matrix such as blood, serum, milk, has been a road blocker. Here we introduce a simple, rapid formation of an anti-biofouling coating onto several electroactive surface areas present on a single chip simultaneously. Using such a multiplexed surface, we were able to investigate the optimum working conditions on-chip. Concentrating on two individual bioassay platforms for stress biomarkers, haptoglobin and cortisol, we demonstrate the broad applicability of the developed universal platform with excellent performance in bovine serum and correlation with conventional ELISA using milk samples.

Until now there is no systematic study on the effect of the substrate composition on the hydrogen silsesquioxane (HSQ) electron beam lithography (EBL) patterning process. We investigate arrays of line structures with varying width and spacing, starting at 10 nm, exposed at varying dose, and developed by salty NaOH and TMAH developers on group IV semiconductor substrates. We demonstrate that the HSQ EBL process on Ge is much more limited in achieving the smallest obtainable features, their uniformity, and fidelity, in comparison to Si. Monte-Carlo simulations of the e-beam to substrate interactions from Si and Ge, through epitaxial Ge/Si layers on Si, to GeOI (Germanium-on-insulator) suggest that the limitations seen are directly linked to back-scattered electron (BSE) generation. As predicted by the simulations and shown experimentally, improved fidelity and resolution of the features can be achieved by minimizing the thickness of the Ge-containing layers and by using high incident (100 kV) EBL systems. Finally, from a metrology perspective it is demonstrated that although line patterns may appear resolved in SEM images, the variation in the brightness across neighbouring lines is a key parameter in understanding the resist clearance between lines that will affect the next etching step for pattern transfer onto the underlying substrate. These results are important for patterning high-density line structures and nano-device engineering as required for realising scalable spin-qubit architectures based on gate-defined quantum dots in semiconductors.

Until now there is no systematic study on the effect of the substrate type on the hydrogen silsesquioxane (HSQ) electron beam lithography (EBL) patterning process. We investigate arrays of line structures with varying width and spacing, starting at 10 nm, exposed at varying dose, and developed by salty NaOH and TMAH developers on group IV semiconductor substrates. We demonstrate that the HSQ EBL process on Ge is much more limited in achieving the smallest obtainable features, having optimal uniformity and fidelity, in comparison to Si. Monte-Carlo simulations of the e-beam/substrate interactions for "pure" Si and Ge substrates, and varying content Ge/Si epitaxial layers on Si, suggest that the limitations seen are directly linked to back-scattered electron (BSE) generation. As predicted by the simulations and shown experimentally, improved fidelity and resolution of the features can be achieved by minimizing the (BSE) generation coming from the Ge contribution in the substartes. Finally, from a metrology perspective, it is demonstrated that although line patterns may appear resolved in SEM images, the variation in the brightness across neighbouring lines is a key parameter in understanding the resist clearance between lines, that will affect the next etching step for pattern transfer onto the underlying substrate. These results are important for patterning high-density line structures and nano-device engineering as required for realising state-of-the art laterally stacked group IV multi-channel field effect transistors (FETs).

Miniaturization is the trend to manufacture ever smaller devices and this process requires knowledge, experience, understanding of materials, manufacturing techniques and scaling laws. The fabrication techniques used in semiconductor industry deliver an exceptionally high yield of devices and provide a well-established platform. Today, these miniaturized devices are manufactured with high reproducibility, design flexibility, scalability and multiplexed features to be used in several applications including micro-, nano-fluidics, implantable chips, diagnostics/biosensors and neural probes. We here provide a review on the microfabricated devices used for biology driven science. We will describe the ubiquity of the use of micro-nanofabrication techniques in biology and biotechnology through the fabrication of high-aspect-ratio devices for cell sensing applications, intracellular devices, probes developed for neuroscience-neurotechnology and biosensing of the certain biomarkers. Recently, the research on micro and nanodevices for biology has been progressing rapidly. While the understanding of the unknown biological fields -such as human brain- has been requiring more research with advanced materials and devices, the development protocols of desired devices has been advancing in parallel, which finally meets with some of the requirements of biological sciences. This is a very exciting field and we aim to highlight the impact of micro-nanotechnologies that can shed light on complex biological questions and needs.

Dopant incorporation in Si can be done in situ during epitaxial growth, or ex situ for localised material modification from a variety of sources including ion, solid, liquid, or gas. Gas-phase doping has the advantage that it does not require a thin film deposition, it is more effective at entering tight spaces than a liquid, and it is less damaging and more conformal than a beam-line ion implant. In this work, we apply arsine (AsH3) gas at approximately atmospheric pressures in order to n-type dope three-dimensional (3D) Si device structures. It was observed that the gas-phase doping can be either corrosive or gentle to thin-body Si depending on the process conditions. Initial doping processes caused damage to the Si due to etching, but after process optimisation, the structural integrity of the Si nanostructures could be maintained successfully. Moreover, it was noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar thin-body structures like fins or nanowires, due to unwanted Si etching. Overall, we found that gas-phase doping with AsH3 could provide >1020 cm−3 electrically active As concentrations. This high As incorporation makes gas-phase doping very attractive for future gate-all-around devices, where the space between features will decline with continued transistor scaling.

The advent of high surface-to-volume ratio devices has necessitated a revised approach to parameter extraction and process evaluation in field-effect transistor technologies. In this work, active doping concentrations are extracted from the electrical analysis of Si nanowire devices with high surface-to-volume ratios. Nanowire resistance and Si resistivity are extracted, by first extracting and subtracting out the contact resistance. Resistivity (q) is selected as the benchmark parameter to compare different doping processes with each other. The impacts of nanowire diameter scaling to 10 nm and of nanowire spacing scaling to <20 nm are extracted for monolayer doping and beam-line ion implantation. Despite introducing significant crystal damage, P beam-line ion implantation beats allyldiphenylphosphine (ADP) P monolayer doping with a SiO2 cap in terms of lower Si resistivity and higher dopant activation, with dependencies on the nanowire width greater than on nanowire spacing. Limitations in ADP P monolayer doping with a SiO2 cap are due to the difficulties in dopant incorporation, as it is based on in-diffusion, and P atoms must overcome a potential barrier on the Si surface. Published by AIP Publishing.

The emergence of miniaturized and integrated Power Supply on Chip (PwrSoC) and Power Supply in Package (PwrSiP) platforms will be enabled by the application of thin-film, integrated magnetics on silicon. A process flow for, and the design of, a thin-film coupled-inductor, switching at 60MHz, is described. Based on the large signal characterization data, measured up to 100MHz,, the efficiency of the inductor is calculated to be 91.7% for a power of 0.5W.

The performance evaluation of a multi-channel transmitter that employs an arrayed reflective electroabsorption modulator-based photonic integrated circuit and a low-power driver array in conjunction with a multi-channel receiver incorporating a pin photodiode array and integrated arrayed waveguide grating is reported. Due to their small footprint, low power consumption and potential low cost, these devices are attractive solutions for future mobile fronthaul and next generation optical access networks. A BER performance of <10(-9) at 10.3 Gbit/s per channel is achieved over 25 km of standard single mode fibre. The transmitter/receiver combination can achieve an aggregate bit rate of 82.4 Gbit/s when eight channels are active.

Highly integrated electronic driver and receiver ICs with low-power consumption are essential for the development of cost-effective multichannel fiber-optic transceivers with small form factor. This paper presents the latest results of a two-channel 28 Gb/s driver array for optical duobinary modulation and a four-channel 25 Gb/s TIA array suited for both NRZ and optical duobinary detection. This paper demonstrated that 28 Gb/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Ω, without degrading the signal quality. To the best of our knowledge, this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 × 25 Gb/s TIA shows a good sensitivity of -10.3 dBm average optical input power at 25 Gb/s for PRBS 2 31 -1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process.

Embedded metrology is the provision of metrology on the manufacturing platform, enabling measurement without the removal of the work piece. Providing closer integration of metrology upon the manufacturing platform can lead to the better control and increased throughput. In this work we present the development of a high precision hybrid optical chip interferometer metrology device. The complete metrology sensor system is structured into two parts; optical chip and optical probe. The hybrid optical chip interferometer is based on a silica-on-silicon etched integrated-optic motherboard containing waveguide structures and evanescent couplers. Upon the motherboard, electro-optic components such as photodiodes and a semiconductor gain block are mounted and bonded to provide the required functionality. The key structure in the device is a tunable laser module based upon an external-cavity diode laser (ECDL). Within the cavity is a multi-layer thin film filter which is rotated to select the longitudinal mode at which the laser operates. An optical probe, which uses a blazed diffracting grating and collimating objective lens, focuses light of different wavelengths laterally over the measurand. Incident laser light is then tuned in wavelength time to effectively sweep an ‘optical stylus’ over the surface. Wavelength scanning and rapid phase shifting can then retrieve the path length change and thus the surface height. We give an overview of the overall design of the final hybrid photonic chip interferometer, constituent components, device integration and packaging as well as experimental test results from the current version now under evaluation.

Non-destructive testing and online measurement of surface features are pressing demands in manufacturing. Thus optical techniques are gaining importance for characterization of complex engineering surfaces. Profilometers based on the laser scanning confocal microscopy can provide non-contact, fast measurement with high lateral and axial resolution. In this work we present the optical design of a lateral scanning probe using a broadly tuneable laser (1500-1600 nm) source in the IR region using Zemax optical design software. The optical probe being one of the main constituents of integrated optic measurement system critically determines the performance of the original metrology sensor system. Various approaches of reduced device dimension have been investigated without compromising the optical performance enabling the probe system suitable for embedded metrology application. The optimization and analysis revealed that the diffraction limited imaging resolution can be achieved using simple achromatic relay lenses and the objective over the entire field of view.

To realise novel, low-cost, photonic technologies that can support 100Gb/s Ethernet in next-generation dense wavelength-division-multiplexed metro transport networks, we are developing arrayed photonic integrated circuits that leverage colourless reflective modulators. Here, we demonstrate a single-channel, hybrid reflective electroabsorption modulator-based device, showing error-free 25.3Gb/s duobinary transmission with bit-error rates less than 1 × 10(-12) over 35km of standard single-mode fibre. We further confirm the modulator's colourless operation over the ITU C-band, with a 1.2dB variation in required optical signal-to-noise ratio over this wavelength range.

Exponentially-increasing demands on the current telecommunication infrastructure are driving the development of next-generation ultra-high-bandwidth network architectures with sufficiently low energy consumptions. Within the scope of the EU FP7 C3PO project, we are developing novel, energy-efficient, colourless photonic technologies for metro applications. The colourless transmitters will leverage reflective photonic integrated circuits, specifically reflective electroabsorption modulator-based phase and amplitude modulators, in conjunction with multi-frequency lasers and low-loss piezoelectric beam-steering optical matrix switches, in order to achieve wavelength reconfigurability without the requirement for tuneable lasers. A specific target is a dynamically reconfigurable metro node which supports duobinary modulation for high dispersion tolerance and efficient spectral usage, to enable 100 Gb/s Ethernet dense wavelength-division-multiplexed transport networks. We report on recent progress towards these metro transport networks, providing the latest system test results obtained using novel hybrid photonic integrated devices.

Within the scope of our EU FP7 C3PO project, we are developing novel, energy-efficient, colourless photonic technologies for low-cost, next-generation dense wavelength-division-multiplexed metro transport and access networks. The colourless transmitters use reflective arrayed photonic integrated circuits, particularly hybrid reflective electroabsorption modulators, and multi-wavelength laser sources, with custom power-efficient driver circuitry. A low-loss piezoelectric beam-steering optical matrix switch allows for dynamic wavelength reconfigurability. Simplifying the required optical and electronic hardware, as well as avoiding the need for expensive, thermally-stabilised tuneable lasers, will yield cost and energy savings for data switching applications in future metro, access, and datacentre interconnection networks. We report on recent advancement towards these low-power optical networks, providing the latest systems results achieved with key enabling hybrid photonic integrated devices and electronic driver/receiver arrays for our targeted applications.

The ICT-APACHE research project is focusing on the development of cost-effective, compact, scalable and agile integrated components capable of generating, regenerating and receiving multi-level encoded data signals for high capacity (>;100 Gb/s) WDM optical networks. APACHE technology relies on InP active, monolithic chips, hybridly integrated on silica-on-silicon planar lightwave platforms in order to achieve cost-efficiency, high yield, low power consumption and device scaling beyond the level commercially available today. The APACHE integration approach is implemented in a two-dimensional plan, horizontally and vertically, in order to enable multi-functionality and increased capacity, respectively. The final goal of the APACHE project is the fabrication of integrated arrays of transmitters, receivers and regenerators that will operate with 100 Gb/s OOK, DPSK and DQPSK modulated signals, allowing for 1 Terabit/s on-chip capacity. In this paper, we will review the latest results from the system-level characterization of the developed components and will outline the roadmap for future endeavours.

Higher levels of optical integration are essential for next generation higher capacity systems. The requirements of higher capacity, lower footprint and reduced cost all lead to the need to integrate. However, this integration must be achieved without loss of performance. Hybrid integration is a key enabler in achieving these objectives. This paper describes one approach for hybrid integration where the best in class device technologies for actives and passives are integrated to produce a multiplicity of integrated devices using the same basic building blocks.

We investigate the performance of a large-scale, silica-on-silicon photonic integrated circuit for multiformat signal processing, and we experimentally demonstrate wavelength-conversion of (differential) quadrature phase-shift keying [(D)QPSK] signals. The circuit exploits phase-incoherent techniques to decode the input signal and to phase remodulate two phase-shift-keying components before combining them in a common QPSK output stream. Error-free wavelength conversion with 4-dB power penalty is reported at 44 Gb/s.

Simultaneous dual-channel OOK and DPSK regeneration at 21.328Gb/s using a single monolithic quad-SOA array hybridly integrated on a silica-on-silicon PLC is demonstrated. The transmission performance of the regenerated signals was evaluated up to 950 km.