The important method of bonding wafers to wafers or die to wafers has been discussed in an earlier chapter. In this chapter, we will examine the formation and filling of through-silicon vias (TSVs) and the post-bond process of thinning waferto-wafer pairs to further process TSVs and build metallization on the final exposed surface. In the section on wafer thinning, the hydrogen-induced splitting of thin silicon layers developed for silicon-on-insulator (SOI) will also be described. In a sense, this is a deviation from the basic processes to stack wafers or dies, but it describes a method to create a type of 3D, which was first envisioned in the 1980s, namely “stacked complementary metal-oxide semiconductor (CMOS)”. Finally, we will comment on processing with handle wafers and mention some of the current methods and areas of research to make this a more cost-effective way of transferring device layers.

Novel porogen loaded ultraviolet (UV) curable materials are being developed to reduce the k value while improving on the mechanical properties of the dielectric for high performance interconnects. In this work, we look at the sensitivity of such a k=2.3 dielectric to the various unit processes on both blanket and single level builds. Within each unit process, a few parameters were studied for their impact on k value and other related parameters. An integrated flow was then developed and the Resistance*Capacitance (RC) product was determined to correlate to the damage from the unit processes.

Die-to-wafer (DtW) stacking offers a yield advantage over wafer-to-wafer (WtW) and system-on-a-chip (SoC) if testing can identify good die and reduce stacking of good and bad die pairs. In this study, an SoC is broken into two equal areas to form a 3D system, and best case yields of DtW and WtW is compared. Testing need not be perfect to realize significant yield advantage with DtW.

We have developed a novel dual phase-modulated Ni silicide for Schottky barrier and series resistance reduction in dopant-segregated source/drain (DSS) n-MOSFETs. Using pre-silicide N2 + implant (thereafter N-implant), it is possible to selectively form interfacial epitaxial Si-rich NiSi2, reducing electron Schottky barrier(SB) from 0.7 eV to 0.34 eV while maintaining a low resistive bulk NiSi, at the same silicide formation temperature. Dual phase-modulated NiSi shows enhanced thermal stability up to 750degC, low rhos of 26 muOmegacm and SB modulation DeltaphiBn = 0.36 eV (expected 81% reduction in contact resistance Rc). Saturation gm for phase-modulated N-modulated DSS n-FETs shows 32% improvement over control NiSi with 22% reduction in series resistance Rext, while still maintaining CMOS integratability.

Dual damascene structures were formed and tested at various trench depths on 300 mm wafers in order to compare etch stop layers of silicon carbide and an organic polymer material with a dielectric constant of 3.2. The metal 2 trenches were filled with Ta and Cu, inlaid and tested at various stages of etch. It has been reported [1] that while damascene structures made with this etch stop material realized reductions in Keff, they exhibited lower intralevel breakdown voltage. The organic etch stop layer exhibited more leakage current as the trenches landed than did the SiC. Ramped voltage breakdown results were similar for the SiC and organic layers except at the tighter pitch and the longest over etch. TDDB lifetimes at 300oC and 1.3 MV/cm were ranked unlanded>SiC etch stop>organic etch stop.