This paper presents an OIF CEI-1125G-XSR compliant short-reach SerDes with data rate from 9.8 to 113Gb/s PAM4/NRZ, implemented in 3nm finfet technology. The quarter-rate source-series terminated (SST) transmitter is im-plemented with 2UI-delay based MUX, supply adjusted and impedance calibrated DAC driver to maintain constant TX swing across PVT. The receiver utilizes a unique AC-coupling-based method before and after single-stage CTLE with 4 edge and 12 data samplers. The design has a standard 3 taps FFE and an optional 6 taps FFE, as well as continuous adapted RX CTLE to track temperature drift and achieve BER<le-14 below 8dB and <le-12 for loss up to 10dB on both 2D and advanced 2.5D CoWoS package.
This paper introduces a digital dynamic vision sensor (DVS) with single-photon avalanche diode (SPAD). The sensor operates in a fully digital manner, eliminating circuit noise and non-uniformity. To provide a motion-adaptive optimum frame rate and minimize vibration-event noise (VEN) caused by sensor vibrations, the sensor generates multiple events via quantized delta (QD) signal. Thanks to the QD, the sensor detects the relative speed of moving objects, adjust the frame rate accordingly, and filter out VEN, thereby allowing only essential events from the objects. Furthermore, the sensor incorporates event-driven threshold control (EDTC) logic to ensure the optimal number of events. The EDTC and VEN filter offers data reduction of 72.8% and 64.5%, respectively.
This paper presents a 20-Gb/s/line current-mode transceiver for dense short-reach on-chip interconnect. The transceiver achieves a systematic crosstalk cancellation (XTC) by balancing the crosstalk induced by capacitive and inductive coupling. As a receiver frontend, a current-sensing amplifier is designed with an optimum input resistance value for XTC. Without any additional circuits for XTC and equalization, the transceiver implemented in a 40nm CMOS technology shows an energy efficiency of 246fJ/b and an edge bandwidth density of I3.3Tb/s/mm, even with shield-less $1.5-\mu \mathrm{m}$ pitch and I-mm length channels.
2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale performance had not been proven yet. This work demonstrates contact length (Lc) scaling while holding a low contact resistance (R C ) down to 11 nm. Channel length $(\mathrm{L}_{\text{CH}})$ scaling shows I ON can increase down to at least 12 nm with low Rc. The very scaled $(\mathrm{L}_{\text{CH }}=19$ nm and $\mathrm{L}_{\mathrm{C}}=12$ nm) Mos2 transistor with Sb-based metal contact has current density of ~1130 μA/μm at $\mathrm{V}_{\text{DS}}$ = 1 V, and a low $\mathrm{R}_{C}$ of ~ 190 Ω.μm. These scaled transistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing (S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to $\mathrm{L}_{\text{CH}}=12\text{nm}$ .
A dense 6T CAM implementing exact and approximate search for sequence alignment is presented. Conventional binary CAM (BCAM) returns a match when the search and stored strings match exactly, approximate CAM (A CAM) returns a match when the hamming distance (HD) between the search and stored strings is within some tolerance. Using a 6T 28nm SRAM bitcell, high density (2.54 Mb/mm 2 ) is achieved, the macro operates up to 200MHz and consumes 0.77fJ/search/bit (BCAM) and 2.37fJ/search/bit (ACAM).
The software-defined VGA image sensor adapts to fast changes in the scene, both locally and globally, by taking advantage of programmable-size/speed super-pixels and scalable-rate SAR ADCs, respectively. Each super-pixel includes up to 8×8 pixels exposed in a rapid sequence within one frame period, yielding a 64x maximum boost of the exposure rate over the output rate, without the corresponding increase in the ADC power. At 360fps readout, this corresponds to over 23,000 exposures/s while using only 24.5mW, and comes at the cost of moderately lower local resolution, only in the regions with the fast changes in the scene. The 54fJ-FoM SAR ADC allows for scaling down to the 30fps ‘slow’ mode, yielding an additional factor of 12x savings in the output data and camera digital power, and 30% savings in the ADC power.
A neural radiance field-based path planning (NeRF-PP) processor, NeRF-Navi, is proposed for accurate, fast and energy-efficient 3D navigation with 3 key features: 1) dual attention neural path sampling (DANPS) engine for energy-efficient NeRF-PP acceleration, 2) approximate-accurate (A 2 ) core with error-compensable reduction tree (ECRT) and bit sparsity boosting logic (BSBL) for low power computation, 3) outlier channel bit-offloading core (OCBOC) for low-latency. NeRF-Navi is fabricated in a 28nm CMOS process and evaluated in 3D real-world maps. As a result, the fabricated NeRF -Navi processor successfully demonstrates real-time NeRF-PP on edge devices consuming only 93.6-202.9µJ/task with 0.57-1.39 ms latency at 1.1V and 200MHz.
Single photon avalanche diode (SPAD) is a key technology in light detection and ranging (LiDAR) sensors, which are gaining prominence as next-generation image sensors. We designed SPAD with high photon detection efficiency (PDE) using a backside-illuminated hybrid bonding 3D-stacked technology. This is aimed at developing a LiDAR sensor with good depth accuracy. We achieved a PDE of 28% at $\lambda= 940\text{nm}$ and a low-level dark count rate (DCR) by applying the trench guide (TG) and the small lens array (SLA) structure and optimizing pixel design. As a result, we achieved a depth accuracy of less than 0.4% up to 10m.
The area-efficient Transformer accelerator exploiting matrix redundancy is presented with four features: 1) A proposed basis-vector decomposition sparing 25.5x model storage for Transformer like Bert-Base, allowing full on-chip inference on devices with about 13MB memory like smartphones, at only 1.28% accuracy loss. 2) An area-efficient self-programming LUT-assisted computing cell by result prefetch; 3) A unified task-insensitive core supporting fast decomposed computing, resulting in a remarkable 73% energy saving; 4) A NoC design facilitating hybrid data reuse to reduce communication. It achieves 4.35 $\text{TOPS} /\text{mm}^{2}$ dense area efficiency, 4 times than the state-of-the-art counterpart at same fabrication level. It also demonstrates 213%-429% higher overall energy efficiency.
This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier 2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZO/Si SRAM is demonstrated with ultra-high density of 4T footprint and 51% reduced static power. In addition, IGZO 2T0C DRAM is integrated in tier 3, which achieves SRAM-DRAM data transfer with record-low latency (<10ns) and energy (2.26fJ). The M3D-SD (with a minimum VDD of 0.35V) can successfully store the data to IGZO 2T0C DRAM and restore to the hybrid IGZO/Si SRAM after 5000s power off. This work provides a novel M3D platform to boost the memory hierarchy performance.
We have successfully developed an innovative barrier metal (BM)-less metal gate scheme with high cell reliability for the 8th generation 3D NAND flash memory. This scheme allows the memory cells to significantly lower the wordline resistance by 30%, enabling a dramatic scale-down in the lateral dimension of a multi-pillar block architecture in 3D NAND. In addition, both cell interference and vertical charge loss can be enhanced by increasing fluorine (F) passivation at the trap sites in the blocking oxide (BOX). Ingenious technologies are developed to suppress degradations originating from the work function change and increased F concentration in tungsten (W) gates. Finally, enhanced cell reliabilities, inclusive of high cycle endurance and long term retention, can be acquired for the 8th generation 512Gb 3D NAND product. Our BM-less metal gate structure provides a novel approach to designing highly competitive future-generation 3D NAND flash memory.
This paper presents a 20Gb/s/pin single-ended PAM-4 transceiver with advanced switching jitter compensation (SWJC) technique. The SWJC operates independently of equalization, hence further improving timing margin from 0.26UI to 0.39UI at a Ie-I2 BER. The proposed pre-channel SWJC at a transmitter side minimizes switching jitter (SWJ) of middle eye, modulating the transitions of top and bottom eyes in a beneficial way for SWJC at a receiver side. Ultimately, along with the proposed SWJC technique, the timing margins improved by SWJC at a receiver side are further increased, having overheads only 1.6% in power and 0.22% in area.
Novel 3D DRAM architectures with 2T0C IGZO gain cell and bit-cost-scalable 3D array process are proposed and demonstrated for the first time. The unit cell is composed of one gate-around (GA) FET and one channel-around (CA) FET to form the 2T0C memory device, where the GA FET and CA FET serve as the write transistor and the read transistor for the DRAM cell, respectively. To verify the possibility of this 3D stacking architecture, we demonstrate the GA IGZO FET by top metal gate with IGZO channel structure, and the CA IGZO FET by bottom IGZO gate with IGZO channel. The integrated 2T0C 3D DRAM memory cell shows excellent device characteristics with>180 second data retention time and endures>1000 second DC stress on the write and read transistors w/o memory window closure. The proposed backend-of-line compact 2T0C DRAM cell features small footprint, bit-cost scalable 3D array, fast write/read, and good reliability, which is promising for future high density embedded memory applications.
For the first time, we demonstrated high-performance Ge-doped In 2 O 3 (IGeO) thin film transistors (TFTs). Through comprehensive understanding of Ge-induced oxygen vacancy (Vo) consumption and crystallization mechanisms, the Vo generation is actively suppressed while increasing its crystallinity. The proposed IGeO TFT with fractional Ge doping (atomic concentration ~0.4% by SIMS) presents an enhanced reliability (Δ Vth = 10 m V, +4 V for 3600 s) with high mobility (µ FE = 62.7 cm2 V −1 S −1 ), which makes it a promising way to overcome the mobility/reliability tradeoff in In 2 O 3 -based TFTs.
We present a complete neural compact model (NCM) that can be used in industry for the first time. This supports not only the features of the standard PDK but also the new features that can vary the process conditions in SPICE such as TCAD simulation. Hence, we dub this “Technology Design Kit (TDK)” to distinguish it from standard PDK. With TDK, we enhanced AC performance by 5% and reduces the optimization time by 45,000 times compared to traditional DTCO. TDK will be a new industry standard for the emerging devices in the future.
We demonstrate a high performance back-end-of-line (BEOL) compatible tungsten (W)-doped In 2 O 3 channel (IWO) dual gate (DG) field-effect transistor (FET) with ultra low-leakage current $<10^{-15}\ \ \mathrm{A}/\mu \mathrm{m}$ and high $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}}$ ratio of $5.8\times 10^{11}$ at 2.5V overdrive $(\mathrm{V}_{\text{ov}})$ . In addition, the IWO DG FET demonstrates a record low negative bias temperature instability (NBTI) of 7.2mV, record low hot carrier degradation (HCD) of 63mV and a low positive bias temperature instability (PBTI) of 85mV at 1V $\mathrm{V}_{\text{ov}}$ which makes IWO DG FET a potential candidate for realizing high density embedded-DRAM for last-level cache (LLC). Furthermore, we develop a comprehensive modeling framework for assesing the reliability of amorphous oxide semiconductor (AOS) channel FETs which can provide insights into the threshold voltage $(\mathrm{V}_{\mathrm{T}})$ instability mechanisms and help design appropriate mitigation strategies.
This paper proposes a Transformer-based processor supporting energy-efficient fine-tuning with batch-iteration-matrix multi-level optimizations. It has three key features: 1) An exponent-stationary re-computing scheduler (ESRC) reduces 44.2% of the storage requirement for each batch. 2) An aggressive linear fitting unit (ALFU) saves 47.4% of the computations in each iteration. 3) A logarithmic domain processing element (LDPE) decreases 36.3% of energy for matrix multiplications (MM) in fine-tuning. The proposed Transformer processor achieves an energy efficiency of 54.94TFLOPS/W. It reduces fine-tuning energy by 4.27× and offers 3.57× speedup for GPT-2.
As the transistor area reaches the atomic scale, many technical challenges have occurred, jeopardizing the lifespan of DRAM scaling, of which word line (WL) resistive defects and Row hammer (R/H) failures are two of the most important quality problems. This paper introduces an innovative process technology to realize a high-purity and low-resistance cell WL that can solve two critical hurdles simultaneously, enabling the DRAM node of 12 nm and beyond. This technology verified a decrease in WL resistance by ∼50% and a two orders of magnitude improvement in R/H fail bits. In addition, by reducing interface trap density (Nit), significant enhancements in the on/off characteristic window and air transportation defects were obtained.
In this work, for the first time, the Flip FET (FFET), a novel stacked transistor technology with self-aligned active and interconnects on both sides of wafer, is proposed and experimentally demonstrated. Two layers of transistors are formed on the same active and back-to-back stacked, featuring a much more manufacturing-friendly process flow with lower aspect ratio (AR) than CFET. Standard cell (STC) libraries with minimum 2.5 track height (2.5T) design are established, proving further scaling possibility and better routability over CFET. Benefited from the dual-side process, FFET also has better design flexibility with no restriction on N/P polarity for each transistor layer, enabling a bipolar SRAM with further 12% area reduction over CFET SRAM and at least 35.9% over FinFET SRAM, respectively. Meanwhile, based on fins, FFET outperforms CFET with 21.5% higher frequency at iso-power and 45.0% lower power at iso-frequency. Furthermore, for nanosheet-based ones, FFET shows extra benefits over CFET with larger nanosheet width (W NS ), with 14.5% higher frequency at iso-power at the same footprint. New concepts of dual-side interconnects are introduced and the P&R result of a RISCV321 core further validates the superiority of FFET with more than 31.3% area reduction compared with CFET.
