Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.

In this work, the lateral etching of the sacrificial high density plasma (HDP) oxide by anhydrous vapor HF (AVHF) together with ethanol vapor is characterized for SiGe microelectro-mechanical systems (MEMS) structures. An extensive design of experiment (DOE) is carried out to study the impact of the process conditions on etch rate (ER) and within wafer uniformity (UWiW). Two wafer level automated techniques, critical dimension scanning electron microscopy (CD SEM) and high resolution profiler (HRP), are compared to replace the manual inspection method performed at die level. It is found that each 25Torr increment in process pressure doubles the ER in the 75 Torr - 125 Torr range. Each 150sccm increment in AVHF flow rate increases the ER 1.3~1.5 times in the 300 sccm - 600 sccm range. Based on the reproducible ER (~80 nm/min) and the UWiW (~10%) of the process of record (POR) as measured by CD SEM, a statistical process control (SPC) is set up for this process condition.