Semiconductor manufacturing is a resource and energy-intensive industry with a substantial environmental footprint. To address the footprint, we present a methodology for quantifying the environmental impact of semiconductor unit processes using the Environmental Footprint 3.1 Life Cycle Impact Assessment (LCIA) framework, focusing on identifying improvement opportunities in process steps with less sensitivity to defects. We apply this methodology to backside wet cleaning by proposing an alternative single-wafer process that adopts ozonated chemistries. The assessment used primary data from imec’s 300 mm pilot line. Results show that the proposed process reduces the total environmental footprint by 55% compared to the baseline Spin Cleaning with Repetitive use of Ozonated water and Diluted HF process. Key reductions include 67% less electricity for cleaning, 59% less HF use, and a 31% reduction in ultrapure water consumption. When scaled to a facility producing N28 Logic wafers at 50,000 wafer starts per month, with 46 backside clean steps per processed wafer, the process achieves annual savings of approximately 4 million kWh of electricity and 28 million liters (28,000 m3) of tap water per year. A sensitivity analysis revealed that replacing fossil-based electricity with hydroelectric power further reduces total environmental impacts by up to 63%, emphasizing the benefit of combining process innovation with renewable energy sourcing.

Wafer-to-wafer Cu/SiCN hybrid bonding at 200 nm pitch relies on surface-diffusion-driven Cu "bulge-out," as elastic expansion during post-bond anneal becomes negligible at these dimensions. The statistical variation of bulge-out therefore directly impacts yield. Using a dedicated 300 mm test vehicle with top-down AFM analysis and EBSD correlation, bulge-out was quantified as a function of pad pitch (200-500 nm), thermal budget (200-450 °C), and Cu microstructure. Bulge-out increases with anneal temperature up to ~350 °C and then saturates. For cavity-to-pad size ratios over 0.7, bulge-out scales with pad size and reaches median values of ~6 nm at 200 nm pitch after a 200 °C anneal. However, a persistent low-bulge-out tail remains insensitive to thermal budget and is shown by EBSD to originate from <111>-oriented pads. Implementing fine-grained Cu eliminates this tail and shifts the full bulge-out distribution upward by several nanometers, demonstrating that Cu microstructure engineering enables robust gap closure at 200 nm pitch and reduced thermal budget.

The newly developed tin-indium (Sn-In) electrolyte enables the electrochemical deposition of eutectic and near-eutectic Sn-In alloys containing 45-55 wt.% indium. The reflow process was successfully conducted at temperatures below 150 degrees C, approaching the eutectic melting point of Sn-In and remaining lower than the melting temperature of pure indium. Additionally, the results of the preliminary bonding tests are presented, demonstrating the potential of this electrolyte for low-temperature assembly applications.

We have successfully performed wafer-level ( 300 mm) fabrication of highly (111) oriented nanotwinned copper (nt-Cu) Redistribution layers (RDL) using through-resist electrochemical deposition on barrier/seed combinations such as TiW/Cu, TaN/Cu, and TaN/Ta/Cu. We have examined physical-chemical properties of nt-Cu and explored possible challenges in post-plating processing of these structures. After photoresist removal, nt-Cu lines were analyzed using Scanning electron microscopy (SEM) and Focused ion beam (FIB) techniques. Within wafer (WIW) and within die (WID) feature height uniformity were measured using profilometry and Cu losses in the plated lines upon wet-etch of the Cu seed were examined using automated SEM measurements.

We investigated chemical mechanical polishing (CMP) of indium, with the goal of obtaining indium bond pads for later cryo-3D integration of quantum computing-related chips, through bonding between these bond pads and indium bumps. Higher removal rates were obtained with soft CMP pads than with hard pads. The latter led to deep scratching, while this effect was much more limited for soft pad CMP. On patterned wafers, indium is cleared well in structured areas using soft pad CMP, leading to relatively high-quality indium surfaces inside bond pads, although corrosion might be of some concern. Pattern density uniformity was an important factor for within-die deviation in indium clearing time. Dishing was much more limited than in earlier work on indium polishing, while surface roughness was also found to be relatively limited. The obtained indium damascene bond pads may be suitable for 3D die-to-die and wafer-to-wafer bonding through indium pad-to-bump bonding.

We present stacked via and wire resistance predictions to find low resistive via metallization schemes that improve the system performance for sub-2 nm nodes. Implementing Ru vias with Cu wires at EUV patterned levels can give up to 60% resistance reduction. The circuit benefit of using Ru vias is determined with enhanced ring oscillator (RO) simulations. The Ru-Cu hybrid metallization in V2-M5 EUV printed layers gives a 10% frequency improvement as compared to stacks with semi damascene (SD) Ru and dual damascene (DD) Cu. The implementation of the selective Ru on Cu is demonstrated in metal pitch (MP) MP21-MP24 DD structures with yielding chains and vias that meet their resistance target.

This year (2023) marks the 25th anniversary of the “Damascene copper electroplating for chip interconnections” publication by P.C. Andricacos et al [1] detailing the dual-damascene process and Cu superfilling of complex structures. And even though this was neither the only electrochemistry contribution to the semiconductor industry nor the first time to report successful plating of Cu structures, it signaled that electrochemical deposition would play prominent role in downscaling race [2]. The authors described Cu superfilling of a feature having characteristic dimensions of about 1 micron. Since then, electrochemists have focused intensely on electrolyte development, optimization of deposition parameters, and improvements in plating tools and process chambers, which went hand in hand with downscaling of features to be filled. Cu was plated on resistive substrates and alternative seeds, various surface pretreatments were applied, and nucleation and growth phenomena studied [3-6], until the focus shifted to alternative metals, such as Co [7]. While Chemical vapor deposition (CVD) and Atomic layer deposition (ALD) offer viable alternatives to electrochemical deposition (ECD) in fabrication of interconnects having width of several nanometers, new challenges and opportunities in 3D packaging and stacking appeared on the horizon. This field resembles more a ‘landscape’ than a ‘one-way street’ that damascene nano-interconnects were. While on one hand downscaling is gaining momentum here, too, there is also upscaling. For example, electrochemically deposited mega-pillars have diameters and heights exceeding hundreds of microns. More than a decade ago, a competitive race started between chemistry suppliers, tool manufacturers and scientists in the field to achieve bottom-up Cu fill of through-Si-vias (TSV) [8], structures meant to provide interconnections between vertically stacked integrated circuits. These structures had characteristic sizes an order of magnitude larger than the ones described in [1]. After demonstrating that superfilling of TSV was indeed possible, it became imperative to satisfy a plethora of production-line requirements, such as optimization of plating time or control of the so-called Cu pumping, a plastic deformation of Cu upon annealing. Plastic deformation leads to an uneven top surface and challenges in stacking layers on top of each other and is, therefore, undesirable. Today, researchers are contemplating possible benefits of the plastic deformation in Cu structures to establish a more robust and reliable Cu-to-Cu bonding process. Achieving defect-free fill of features was never the only requirement to be satisfied, but the ability to control plastic deformation in Cu features, or fabricate structures with specific texture, grain size, crystal structure [9, 10] on sub-micron scale, might require more thorough modifications of the current Cu plating processes. We will review this and other current trends in electrochemical deposition for applications in ‘classical’ semiconductor industry. We will also consider possibilities in technologies for Quantum computing, where a new spectrum of non-traditional candidate elements for plating could emerge [11, 12]. There, lessons learned from the downscaling of traditional interconnects could prove very useful. References: [1] P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, IBM J. Res. Develop., 42(5), 567 (1998). [2] K. Rajeshwar and F. Roozeboom, Electrochem. Soc. Interface 16, 11 (2007). DOI 10.1149/2.F01071IF [3] M. Nagar, A. Radisic, K. Strubbe, and P. M. Vereecken, Journal of The Electrochemical Society, 163(12), D3053 (2016). [4] T. P. Moffat, M. Walker, P. J. Chen, J. E. Bonevich, W. F. Egelhoff, L. Richter, C. Witt, T. Aaltonen, M. Ritala, M. Leskelä, and D. Josell, Journal of The Electrochemical Society, 153(1), C37 (2006). [5] L. Yang, T. Atanasova, A. Radisic, J. Deconinck, A. C. West, and P. M. Vereecken, Electrochimica Acta, 104, 242 (2013). [6] L. Yang, A. Radisic, M. Nagar, J. Deconinck, P. M. Vereecken, and A. C. West, Electrochimica Acta, 78, 524 (2012). [7] M. A. Rigsby et al, ECS Trans., 80(10), 767 (2017). DOI 10.1149/08010.0767ecst [8] L. Yang, A. Radisic, J. Deconinck, and P. M. Vereecken, Journal of The Electrochemical Society, 160(12), D3051 (2013). [9] C.-H. Tseng and C. Chen, Cryst. Growth Des., 19(1), 81 (2019). https://doi.org/10.1021/acs.cgd.8b00916 [10] L. Mirkarimi et al, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), Pages 162 – 167. DOI 10.1109/ECTC51906.2022.00036. [11] D. P. Pappas et al, Appl. Phys. Lett. 112, 182601 (2018); DOI: 10.1063/1.5027104. [12] G. Hautier, J. D’Haen, K. Maex, and P. M. Vereecken, Electrochemical and Solid-State Letters, 11(4), K47 (2008).

Selective atomic layer deposition (ALD) of Mo is explored to fill 10nm contacts in a 2 nm node test vehicle. The ALD Mo deposition is highly selective towards the dielectrics (SiO 2 , low-k OSG3.0, SiCN), and deposits selectively on the bottom Ru routing contact layer. Barrierless Mo via fill levels in the range of 10-20nm are obtained without detecting Mo in the dielectrics of the stack. The resistance of the Mo in MP24 vias with aspect ratio (AR) 2 is ~ 50Ω. Further resistance reduction is expected upon removing the top interfacial oxide introduced by an air break during metallization. The reliability shows that stress induced voiding is not observed for the Mo-Cu metallized system. Additionally, the via electromigration failures are only observed in the connecting Cu top trench, leaving the robust ALD Mo vias intact.

Wet surface treatment of InGaAs is crucial for high-performance complementary metal-oxide semiconductor (CMOS) devices as it reduces material loss and oxide formation in the InGaAs layer. In this present study, the surface chemistries of In0.53Ga0.47As during wet chemical etching and the chemical-mechanical planarization (CMP) process in acidic (HCl/H2O2/H2O mixture) and alkaline (NH4OH/H2O2/H2O mixture) solutions were investigated. Elemental oxide formation, surface termination, and stoichiometry after the chemical etching/CMP process were investigated through X-ray photoelectron spectroscopy and atomic force microscopy. In wet chemical etching, the dissolution of the InGaAs elemental oxide was more prominent in acidic HCl mixture solutions compared to alkaline NH4OH mixture solutions. It was observed that the overall surface etching was more aggressive in acidic solution, whereas the alkaline solution provided higher surface roughness (R-a, similar to 7.19 nm, scanning area of 5 mu m x 5 mu m) due to the lower dissolution capacity of indium oxide. The effects of the oxidizer and the slurry pH on the removal rate, Ra, and surface contamination were evaluated after the InGaAs CMP process. A high removal rate (similar to 110 nm/min) and considerably lower surface contamination were obtained using an alkaline slurry (pH 10). A novel InGaAs CMP slurry is developed by adding different ammonium halide salts to the alkaline slurry for improving surface roughness and removal rate. The addition of ammonium halide salts to an alkaline slurry was very effective in achieving a higher removal rate (similar to 175 nm/min) and smoother surface (R-a < 0.6 nm) with lower contamination during the InGaAs CMP process.

The connection of semiconductor devices happens through metal interconnects at the back end of line (BeOL) in integrated circuits. The BeOL consists of multiple metal levels that are vertically connected through small contact holes, or so-called vias. Especially at the lower metal levels, the vias are becoming much smaller in critical dimension, which increases their resistance significantly while more of these vias are needed to make the more complex connections in future device architectures. For these reasons, the vias resistance is becoming the dominating part of the total resistance of the stack and may become the limiting factor in keeping resistance-capacitance delay under control. In this work, the metal-on-metal area selective metal deposition is studied to make low resistive vias. The via is first prefilled with the Ru before performing the Cu metallization of the remainder of the vias and wires. Ru is chosen as the preferred metal [1] because it can be used without a metal barrier (it does not electromigrate) and this provides a large resistance benefit as compared to the Cu metallization which needs a TaN barrier combined with a Co liner. The combination of the different metals for the via (here Ru) and the metallization of wires (here Cu), is called a hybrid metallization scheme. We will discuss the challenges for the Ru selective deposition on the metal (growth area) towards different dielectrics as the non-growth area. The selectivity studies to optimize the Ru chemical vapour deposition (CVD) recipe and surface treatments are performed on blanket level (non-patterned wafers). A small molecule inhibitor dimethylamino-trimethylsilane (DMA-TMS) is used to passivate the dielectric surface which makes the dielectrics less reactive towards the Ru deposition improving thereby the selectivity of the CVD process (see also Fig.a).[2] We demonstrate that the growth rate and selectivity of Ru ASD depend on the CVD process conditions (type of co-reactant and process temperature) and the type of nanopattern (line spaces or via holes).[3] The most selective Ru process found with the line-space pattern (45/45nm line-space width) was also tested in nanoscale patterns with via holes of ~10.5nm.[4] It was found that the Ru growth rates in the patterned structures are enhanced as compared to the blanket substrates. The CVD Ru growth rates are ~ 1.3x higher in line-space nanopatterns as compared to flat metal substrates, and up to 3x higher in the small contact holes.[4] The growth enhancement of the CVD process is beneficial for the technological implementation of the process. The results show that the growth rate and the selectivity are different from the behavior on blankets and are also pattern dependent, which is consistent with a growth mechanism that is based on diffusion in addition to adsorption.[2] Therefore, the metal-on-metal selective deposition process may need to be optimized and adjusted to the patterned structure used in the interconnect application. [1] D. Gall et al , J. Appl. Phys. 2016, 119, p.085101. [2] F. Grillo and J. Soethoudt et al , Chem. Mater. 2020, 32, 22, 9560–9572. [3] A. Kumar Mandal et al , “Ruthenium Area-Selective Deposition for Nano-interconnect Structures: Process and nanopattern dependent selectivity and growth rate” Manuscript in submission 2023. [4] M.H. van der Veen et al , Proc. of the IITC 2021, S7-2. . Figure 1

The dimensional scaling of the back-end of line (BeOL)interconnects is a significant challenge for the deposition and fill of conductive metals in narrow lines and small vias that are needed to connect the semiconductor devices. Especially at the lower and the smaller interconnect levels, the scaling of the copper (Cu) dual damascene is becoming the limiting factor due to the increase in the resistance-capacitance delay. The increase in RC delay results in a degradation of the chip performance. So, while the scaling in the logic device landscape leads to a continuous improvement of the device performance and an increased transistor density, the Cu wiring in the interconnects systems tend to perform worse when scaling down the dimensions. This paper addresses methodologies to continue the scaling of the BEOL interconnects down to small CD’s like 12nm. For this, process and materials innovation are the key to reduce the interconnect area and its resistance.[1] Examples that will be discussed include Cu hybrid metallization and the use of new conductor materials or integration methodologies like metal patterning. In being the workhorse for building multilevel interconnects, the first desired direction is to push and extend the conventional Cu dual damascene metallization to small dimensions. However, extending Cu is not only challenging from a metal fill point of view, but also from the resistance as well as reliability point of view. The ideal metal that could replace the conventional Cu should have a low electrical resistance in scaled dimensions, have a good thermal conductivity, is resistant against oxidation and possesses a high melting point.[2] This melting is a good measure for the ease of electromigration due to metal diffusion where a high melting point would allow for a reliable operation without the need for a barrier material to prevent it to diffuse. This brings Ru, Mo and W in the picture as interesting material to replace Cu in the vias, and potential later in the lines as well. Figure 1 (left) shows the tabulated via and line resistance predictions for Cu and alternative metals to Cu like Co, Ru, Mo and W (method described elsewhere [3]). The red color coding is used to indicate too high resistance values, where green indicates the desired target resistance. The resistance benefit for the use of Ru, Mo or W compared to Cu is clearly visible in the table. An efficient way to introduce a new alternative metal in the Cu interconnect metallization without being too disruptive is using a selective metal deposition for the vias landing on the exposed bottom metal (Fig.1 middle). After the vias are filled using a selective metal-on-metal deposition with a barrierless metal like Ru or W [4,5], the remainder of the structures can be filled using the conventional Cu metallization scheme. This process is called a Cu hybrid metallization scheme. Filling the vias before the Cu line metallization, improves the process window and yield for the Cu gapfill. Challenges for the selective deposition of metals in vias will be discussed. The XTEM in Figure 1 (right) shows a successful example of the metal prefill in a via hole with bottom CD of 14nm. The via is nicely filled with the metal while the top lines in the dielectric that are not connected to vias do not show any non-selective deposition. Even though the vias are becoming more and more critical in the signal routing on a system-on-chip level, the resistance penalty for the Cu lines is unacceptable at small CDs as can be seen in the table in Fig.1. But eventually, the Cu electromigration will set the limit because at 10nm CD copper lines are not expected to meet electromigration requirements anymore [6]. This is then an inflection point to also replace the lines with alternative metals like Ru, Mo or more exotic conductors like binary metals. For these metals, the challenges in the line fill, processing, and integration will be discussed which may lead to the introduction of the so-called semi-damascene module [7] instead of using the dual damascene methodology. [1] J. Clarke et al, IEEE VLSI 2014, p. 176 [2] D. Gall et al, J. Appl. Phys. 2016, 119, p.085101 [3] I. Ciofi et al, IEEE transactions on Electron Devices 2017, 64 (5), p.2306 [5] M.H. van der Veen et al, Proc. of the IITC 2021, S7-2 [4] M. van der Veen et al, Proc. of the IITC 2020, p.16 [6] K. Croes et al, IEDM 2018, p 5.3.1 [7] Zs. Tőkei et al, IEDM 2020, p 32.2.2 Figure 1

The use of eutectic Sn-Cu alloys in packaging applications in microelectronics industry is not something entirely new. However, this alloy was mostly used in large features and fabricated using metal powders and metallurgical deposition techniques. The diameter of an individual grain of the eutectic Sn-Cu powder is typically similar in size to the diameter of pillars or bumps currently used in 3D stacking, and if we were to check its usefulness as a solder on this scale, an alternative manufacturing technique had to be used. We have electrochemically deposited Sn-Cu alloys having up to 10 wt.% Cu and explored its possible benefits when used as a solder in combination with different Under bump metallization (UBM) materials. Sn-Cu alloys were deposited on blanket and patterned coupons, and promising experiments then transferred to a wafer-scale, i.e. Sn-Cu alloys were deposited on 300 mm wafers in an industrial-type plating tool. A typical sample/wafer had a Cu seed with a diffusion barrier (e.g. TiW) underneath and patterned features defined with a photoresist mask. Characteristic dimensions of the patterned features were on the order of mm and cm (lines), (diameter)D50µm × (height)H60 µm (pillars), and D8µm × H15 µm (bumps). Cu, Ni, or Co were used as UBM layers. Chemical composition of deposited alloys has been examined by using X-ray fluorescence (XRF), Micro X-ray fluorescence (Micro-XRF), Inductively coupled plasma mass spectrometry (ICP-MS), and Electron probe microanalysis (EPMA). Surface morphology and the shape of deposited features have been examined using Scanning electron microscopy (SEM) and Laser scanning microscopy (LSM), while thermodynamic properties have been studied using Differential scanning calorimetry (DSC). Within-wafer (WIW) and within-die (WID) height uniformity of the pillars has been analyzed using Falcon 630 Plus tool (Camtek Ltd), capable of capturing heights of all the structures on the wafer simultaneously. The kinetics of Intermetallic compound (IMC) formation have been studied in the number of selected samples by combining ex-situ Focused ion beam (FIB) and in-situ measurements of resistance change of the features during anneal/thermal ageing [1]. We will discuss possible benefits and drawbacks for use of electrochemically deposited Sn-Cu alloy solders in combination with different UBM layers based on these results. References: [1] Lin Hou, Jaber Derakhshandeh, Eric Beyne, and Ingrid De Wolf, “A Novel Resistance Measurement Methodology for in-situ UBM/Solder Interfacial Reaction Monitoring”, DOI 10.1109/TCPMT.2019.2950448, IEEE Transactions on Components, Packaging and Manufacturing Technology. Figure 1

In this work we evaluate low via resistance options in 21 – 24nm pitch structures by comparing Ru, W versus Cu. A bottom barrierless Cu DD metallization is created using a selective TaN deposition. In MP24, this selective barrier Cu metallization system shows up to a 20% via resistance reduction as compared to conventional Cu DD fill with 1.5nm TaN barrier. The via resistance evaluation of the selective barrier Cu in MP21 shows that the system can be an option for further extension of Cu interconnects while keeping the resistance under control. The line and chain resistance comparison towards barrierless DD Ru shows that the SB Cu metallization is competitive in terms of performance and therefore the preferred way forward for MP24 DD structures.

This letter describes the use of area-selective electroless Cu deposition for topography control of Cu-SiCN hybrid bonding pads. The electroless deposition of Cu allows one to obtain protrusions on hybrid bonding Cu pads without further polishing optimization. A recessed Cu pad after chemical mechanical polishing becomes a protrusion after electroless deposition. This indicates that the electroless Cu film was selectively deposited on Cu, without deposition on the SiCN surface. A void-free Cu-Cu bonding interface was observed after annealing at 350 degrees C with an electroless Cu layer at the interface. 100% electrical connection was obtained at 1.4-mu m pitch where the deposition thickness was on target.

The effects of H2O2 on the chemical etching and removal rate (RR) of molybdenum (Mo) were investigated. Static etch rate (SER) and chemical mechanical planarization (CMP) experiments were performed using H2O2-based slurries at different pH levels. X-ray photoelectron spectroscopy (XPS) and potentiodynamic polarization analysis showed the formation of Mo oxides by the reaction between Mo and H2O2. The Mo SER, which increased with H2O2 concentration, supported the dissolution of Mo oxides through the formation of peroxo Mo complexes with H2O2. The CMP removal mechanism was demonstrated by comparing the CMP RR with and without silica abrasives. In addition, the Mo oxidation rate by H2O2 on a millisecond time scale was characterized with chronoamperometry to explain different RRs at pH values ranging from 2 to 8. The CMP RR of Mo was high at pH 2 and pH 10; however, pH 2 showed a lower SER than pH 10, leading to lower surface roughness.

3 formulated etchants were prepared and their etch rates were measured using blanket wafers in order to confirm that the etching reactions on Si 1-X Ge X and Si are controllable. Si 1-X Ge X selective etching with those formulations was also verified using the wafers which had Si 1-X Ge X and Si multi-stacked structures. Cross-sectional transmission electron microscope (TEM) images suggested that the formulations were usable for Si 1-X Ge X selective etching processes.

In this exploratory study, selective tungsten (W) deposition is used before the copper (Cu) metallization steps with the aim to solely fill the via with W. The W deposition is tested on the bottom metal cobalt (Co) or ruthenium (Ru) and shows an excellent selectivity towards the dielectric SiO 2 and dense low-k material 3.0. The via resistance shows up to a 40% reduction for the W-Cu hybrid system compared to a Cu dual damascene (DD) filled via. The material compatibility is tested in a thermal storage study and shows no performance degradation of the bottom barrierless W vias. This feasibility study using a middle of line (MOL) metal shows that a W-Cu hybrid system can be an option for further extension of Cu interconnects while suppressing the via resistance.

Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.

Patterns down to 21nm metal pitch (MP) have been used in the hybrid metallization scheme of Ru via prefill followed by a Cu trench metallization. The via resistance for Ru in hybrid with TaNRu/Cu trench fill is benchmarked to Co and Ru dual-damascene (DD) metallization schemes. At 30nm MP, a 40% via resistance reduction is observed upon introducing the Ru prefill prior to the Cu metallization. The Ru prefill significantly improved the via yield for the Cu metallization in 21nm MP. At this dimension, a 35% lower resistance is obtained with the Ru-Cu hybrid system when benchmarked to Co and Ru full fill with a 1nm TiN barrier. The electromigration of the Ru-Cu hybrid system does not a show a performance degradation, making it a viable scaling scenario for DD metallizations in N5 technologies and beyond.