Recently a demand for further weight reduction and higher efficiency of traction inverters is increasing on our market. To achieve those requests, an enhancement of power density of power modules for traction applications is one of the keys to be successful. This paper describes the electrical characteristics of a newly developed 3.3kV All-SiC with the 2nd generation trench gate SiC-MOSFETs in a new high power package (HPnC), which is suitable for traction applications. This All-SiC module achieves more than twice the power density against a silicon version. In addition, Fuji’s 2nd generation trench gate SiC-MOSFETs enables eliminating SiC-SBDs, which allows further enhancement of power density.

Recently a demand for further weight reduction and higher efficiency of traction inverters is increasing on our market. To achieve those requests, an enhancement of power density of power modules for traction applications is one of the keys to be successful. This paper describes the electrical characteristics of a newly developed 3.3kV All-SiC with the 2nd generation trench gate SiC-MOSFETs in a new high power package (HPnC), which is suitable for traction applications. This All-SiC module achieves more than twice the power density against a silicon version. In addition, Fuji’s 2nd generation trench gate SiC-MOSFETs enables eliminating SiC-SBDs, which allows further enhancement of power density.

We developed 3.3 kV-class silicon carbide superjunction (SJ) MOSFETs and demonstrated their excellent static and dynamic properties. The full-SJ device exhibited ultra-low R on A of 3.3 mΩcm 2 at room temperature (RT) and 6.2 mΩcm 2 at 175 °C. The small reverse recovery charge of SJ devices at RT and 175 °C was realized by injection level suppression. Owing to these advantages, superior total power loss was estimated when the SJ-devices were operated as a half-bridge synchronous rectifier.

Recently main requirements of traction inverters are further weight reduction by downsizing and higher efficiency of power conversion systems. For this reason, enhancing the power density of power modules will be the key to success. In this paper, electrical characteristics for 3.3kV All Silicone carbide(SiC) modules with the 1st generation trench gate SiC MOSFETs and HPnC named High Power Next Core package, which are suitable for traction application, have been presented. In addition, a comparison of PWM simulation results under typical traction conditions between All SiC modules with trench gate MOSFET and Silicon(Si) modules were shown and resulted in a 66% expansion of power density for All SiC module with trench gate MOSFET.

Recently the main requirements of the market are further downsizing and higher efficiency of power conversion systems. For this reason, enhancing the power density of power modules will be the key to succeed. In this paper, electrical characteristics for All-SiC modules with the 2nd generation trench gate SiC MOSFETs have been presented. Moreover, it has been demonstrated that 3 rank extension for inverter capacity could be achieved by using All-SiC modules rather than conventional Si IGBT modules. Therefore, these modules will realize further downsizing and higher efficiency of power conversion systems.

The SiO2/SiC interface quality has a significant effect on the performance of 4H-SiC MOS devices. The introduction of nitrogen to the SiO2/SiC interface is a well-known method for reducing the interface state density (Dit). In this study, we introduced nitrogen to the SiO2/SiC interface by forming SiNx films using atomic layer deposition (ALD) and thus improved the interface quality. O2 annealing with a SiNx interface layer of optimal thickness enhanced the field effect mobility.

We proposed an Schottky barrier diode wall integrated trench MOSFET (SWITCH-MOS) for the purposes of shrinking the cell pitch and suppressing the forward degradation of the body diode. A trench Schottky barrier diode (SBD) was integrated into a trench gate MOSFET with a wide shielding p+ region that protected the trench bottoms of both the SBD and the MOS gate from high electrical fields in the off state. The SBD was placed on the trench sidewall of the {1 (1) over bar 00} plane (m-face). Static and transient simulations revealed that SWITCH-MOS sufficiently suppressed the bipolar current that induced forward degradation, and we determined that the optimum Schottky barrier height (SBH) was from 0.8 to 2.0 eV. The SBH depends on the crystal planes in 4H-SiC, but the SBH of the m-face was unclear. We fabricated a planar m-face SBD for the first time, and we obtained SBHs from 1.4 to 1.8 eV experimentally with titanium or nickel as a Schottky metal. (C) 2017 The Japan Society of Applied Physics

Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss. Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode. Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5p.m was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer. The fabricated 1.2 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current.

Abstract We have investigated the gate current–voltage ( I g – V g ) characteristics of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) and p-MOS capacitors on the 4H-SiC face. The gate current response to a change in gate voltage has a very slow part, which has been considered to be due to slow traps in the oxide near the SiO 2 –SiC interface. However, we found that the slow response can be explained by fast interface traps if the traps have a relatively large concentration. Carrier injection into the interface traps results in a change in the surface potential, and this suppresses the further injection of carriers. This new model can explain many electrical properties such as the constant-current behavior in the I g – V g characteristics, which was confirmed by one-dimensional (1D) device simulation. According to this model, the interface traps will not be occupied up to the surface Fermi level within the general time scale of the measurement. In spite of the arguments described above, slow traps also probably exist near the interface between SiO 2 and SiC.

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low R onA was sustained as V th increases. The R onA values at V G =25 V (E ox =3.2 MV/cm) and V G =20V (E ox =2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm 2 with a lowest V th of 2.4 V, and 3.1 and 4.4 mWcm 2 with a high V th of 5.9 V.

The thermal management of power module is one of the key important issues for power conversion circuit design. SiC power module is expected to give less conduction and switching loss than conventional Si device, which enables to facilitate the thermal management of a power conversion circuit. This paper develops 2in1 Full-SiC power module and studies the applicability for 600V→300V, 15kW DC-DC buck converter. The feasible thermal design of SiC power module to serve rated operation of the converter circuit is discussed based on the elemental experiments. The developed full-SiC power module realized lower loss and smaller converter circuit than conventional-Si power module.

For the realization of a low-carbon-emission society and in terms of energy security, the grid connections of electric power systems are highly desired by applying a smart grid and high voltage DC transmission systems (HVDC). If switching devices with a break down voltage (BV) greater than 10kV are realized, it would be extremely beneficial for the reduction in size and loss of the power electronics components such as a loop power controller (LPC), a static synchronous compensator (STATCOM), and an intelligent solid state transformer (SST). Silicon carbide (SiC) is expected to be a next-generation power semiconductor material because its band gap is three times larger than that of Si. The breakdown electric field of SiC is 10 times higher than that of Si, allowing the thickness of the drift layer in SiC power devices to be 1/10 that of Si power devices. Thus, if an insulated-gate bipolar transistor (IGBT) structure of SiC is used, it will be possible to realize more than 10 kV MOS-controlled switching devices with very low on-resistance [1, 2]. We have been working on a SiC p-channel IGBT with a BV of 10 kV [4] as well as a PiN diode with a BV of 13 kV [5]. For these devices, a high-quality n++ substrate could be used for device fabrication. However, the crystal quality of the p++ SiC substrate for the purpose of fabricating an n-channel IGBT is currently very poor with a high micropipe density and high resistivity using it as a collector. Moreover, the channel mobility for a SiC-MOSFET is still very low compared with that of a Si-MOSFET because of its 10-times higher interface-state density (Dit). To solve these problems related to n-channel SiC-IGBTs, we employed a heavily doped epitaxial p++ layer as a substrate and an implantation and epitaxial MOSFET (IEMOSFET) [5, 6] as a MOSFET structure, which is called a flip-type IE-IGBT. For the substrate, we attempted to fabricate a flip-type wafer utilizing a p++ epitaxial layer as a substrate [1]. First, a 150-mm-thick n–-type drift layer was grown on the Si-face n++ substrate after a buffer layer was formed. After the p+ collector layer was grown, the p++ substrate layer was grown to a thickness greater than 200 µm. Then, we removed the n++ substrate, turned the substrate over, and polished the surface using the CMP process. To overcome the low channel mobility of the SiC-MOSFETs, we proposed the IEMOSFET utilizing the 4H-SiC (000-1) carbon face, which has a high channel mobility greater than 100 cm2/(Vs) [6]. The bottom and top of the p-well of the IE-MOSFET are formed by ion implantation and epitaxial growth, respectively. The smooth surface of the top of the p-well enables high channel mobility. A TCAD simulation was employed to optimize the design of the active area and edge termination to obtain a low forward-voltage drop (Vf) and an ultrahigh breakdown voltage. As a result, we successfully fabricated an IE-IGBT with a low Vf of 5.0 V at 100 A/cm2 with a BV greater than 16 kV [7]. At the same time, we achieved good threshold voltage (Vth) stability and a low current-density dependence on the temperature. An ultrahigh-voltage power module was assembled to evaluate the dynamic behavior of the IE-IGBT and consisted of a tungsten base plate, a DBC base with Si3N4on it, and a copper electrode. The dynamic switching performance of the combination of the ultrahigh-voltage IE-IGBT and PiN diode will be presented. [1] X. Wang, J. A. Cooper, IEEE Transactions on Electron Devices Vol. 57, No. 2, pp. 511-515, (2010) [2] S. H. Ryu, L. Cheng, S. Dhar, C. Capell, C. Jonas, J. Clayton, M. Donofrio, M. J. O’Loughlin, A. A. Burk, A. K. Agarwal, J. W. Palmour, Materials Science Forum Vols. 717-720, p. 1135 (2012) [3] S. Katakami, H. Fujisawa, K. Takenaka, H. Ishimori, S. Takasu, M. Okamoto, M. Arai, Y. Yonezawa, K. Fukuda, Materials Science Forum Vols. 740-742, p. 958 (2013) [4] D. Okamoto, Y. Tanaka, N. Matsumoto, M. Mizukami, C. Ota, K. Takao, K. Fukuda, H. Okumura, Materials Science Forum Vols. 740-742, p. 907 (2013) [5] K. Fukuda, M. Kato, J. Senzaki, K. Kojima, Appl. Phys. Lett. Vol. 84 p. 2088 (2004) [6] S. Harada, M. Kato, K. Suzuki, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai, Technical Digest of IEDM p. 903, (2006) [7] Y. Yonezawa et al., “Low Vf and highly reliable 16 kV ultrahigh voltage SiC flip-type n-channel implantation and epitaxial IGBT”, in Proceedings of International Electron Devices Meeting (IEDM), 2013, pp. 6.6.1–6.6.4.

4H-SiC(000-1) C-face was oxidized in H2O and H-2 mixture gas (H-2 rich wet ambient) for the first time. H-2 rich wet ambient was formed by the catalytic water vapor generator (WVG) system, where the catalytic action instantaneously enhances the reactivity between H-2 and O-2 to produce H2O. The dependence of SiC oxidation rate on the H2O partial pressure was investigated. We fabricated 4H-SiC C-face MOS capacitor and MOSFET by the H-2 rich wet re-oxidation following the dry O-2 oxidation. The density of interface traps was reduced and the channel mobility was improved in comparison with the conventional O-2 rich wet oxidation.

New SiC (Silicon Carbide) power semiconductor modules were developed and applied to the power electronics equipments. 25% of loss in the motor drive inverter is reduced by applying hybrid modules which are composed of conventional Silicon IGBTs (Si-IGBT) and SiC Schottky Barrier Diodes (SiC-SBD). In case of a 20kW inverter for solar photovoltaic (PV) generation, 99% of main circuit efficiency and reduction of size to 25% are realized by applying all-SiC modules using SiC-MOSFETs and SiC-SBDs. Furthermore, we developed a boost chopper using the all-SiC modules for high power PV inverter (Mega solar) application. By applying the boost choppers, the input voltage fluctuation is reduced and 25% of power density is increased.

4H-SiC carbon face flip-type n-channel implantation and epitaxial (IE)-IGBT with an epitaxial p ++ substrate was developed and its switching test was carried out. We were able to achieve an ultrahigh blocking voltage greater than 16 kV, extremely low V on (6.35 V at 20 A), and good temperature stability. The switching operation was achieved by connecting three IGBTs in parallel, with a total I CE of 60 A and V CE 5 kV. The turn-off loss and turn-on loss were about 220 mJ and 120 mJ, respectively at room temperature. They show low switching loss of ultrahigh voltage SiC IE-IGBT and the possibility of large scale module with parallel connection.

Flip-type n-channel implantation and epitaxial (IE)-IGBT on 4H-SiC carbon face with an epitaxial p++ collector layer was investigated. In this study, we employed the IEMOSFET as a MOSFET structure with original wet gate oxidation method, to realize high channel mobility. We were able to achieve an ultrahigh blocking voltage of more than 16 kV, extremely low forward voltage drop of 5 V at 100 A/cm2 and small threshold voltage shift (<; 0.1 V). These characteristics are useful for Smart Grid and HVDC systems, the use of which would realize a low carbon emission society.

The 1200V class silicon carbide Schottky barrier diodes were designed and fabricated. The drift layer resistance was reduced in order to realize low forward voltage drops. Since the low drift layer resistance led to the low breakdown voltage, the avalanche withstanding capability should be enhanced not to cause the destructive breakdown. By means of the optimized device design, we succeeded to realize the low forward voltage drop while maintaining the high avalanche withstanding capability. The forward voltage drops at 200A/cm° were 1.35V at 25°C and 1.63V at 175°C, respectively. The avalanche withstanding capability was more than 3500mJ/cm₂ at 25°C. By substituting SiC-SBDs for Sipin diodes, the estimated total power loss of the module comprised by Si-IGBTs and the diodes was reduced by 35%. We could also confirm that no failures happened after long term reliability tests.

In this paper, we demonstrate the fabrication of SBD utilizing SiC process line specially designed for mass production of SiC power device. In SiC power device process, ion implantation and activation annealing are key technologies. Details of ion implantation system and activation annealing system designed for SiC power device production are shown. Further, device characteristics of SBD fabricated using this production line is also shown briefly.