We developed a new 1200-V reverse conducting insulated gate bipolar transistor with a structure called Schottky and multi-layered anode (a unique carrier injection control approach without lifetime-control) for TOYOTA's 5th generation hybrid electric vehicle and plug-in hybrid electric vehicle systems. The developed devices reduced total losses (conduction and switching losses) by 10% compared to the conventional product. It also reduced the number of parts for the power module and contributed to its 25% size reduction, ultimately contributing to the downsizing of 13% of the power control unit.
In this work, the low-loss reverse conduction and high threshold voltage characteristics are simultaneously demonstrated in 1 kV/10 A $p$ -GaN high electron mobility transistors (HEMTs) on an existing 6-inch process platform, thanks to the combined advantages of the uniquely designed source-controlled p-GaN hybrid structure and improved gate-stack layer. The reverse-conduction turn-on voltage of the resultant device is effectively decoupled from the threshold voltage and gate bias, which is different from the conventional p-GaN gate HEMTs. In addition, superior dynamic performances with nanosecond reverse recovery and switching characteristics are also realized, revealing the notable potentials of the high- $V_{\text{TH}}$ low-loss p-GaN HEMTs for high-power and high-frequency applications.
A novel structure named bipolar mode activation cell (BMA cell) is demonstrated to prevent current crowding in parallel connections of SBD-embedded SiC-MOSFETs during a surge current event. In a BMA cell, where the SBD area is partly filled with p-body to inactivate the corresponding part of SBD, I-V characteristics are uniform for each parallel-connected device under a surge condition. The parallel-connected devices with BMA cell have more than 5 times higher surge current capability compared with the conventional devices owing to the absence of current crowding.
A novel junction termination technique (JTT) is proposed, which combines three techniques of the optimum variation lateral doping (OPTVLD), buried-layer (BL) and high-k (HK). By utilizing the OPTVLD and BL techniques, an ideal electric field distribution is achieved, resulting in excellent cost-performance. Moreover, by adopting a SrTiO 3 film with high permittivity, which induces bound charges that respond automatically to the deviated charges, an extraordinary anti-charge-deviation ability is obtained for the first time. According to the simulation results, in comparison with the conventional JTT structure without the SrTiO 3 film, the proposed one gets better process windows increased by 93.3%, 73.9%, 73.9% and 61.3%, with respect to the deviation factors of dose, temperature, heating time and interface charge, respectively. Moreover, since the proposed JTT can be realized by BiCMOS-compatible process, it is budget-friendly and highly feasible.
This paper presents the development and evaluation of a 1.2 kV 4H-SiC Split-Gate (SG) MOSFET with a deep P-well structure that effectively reduces the maximum electric field in the gate oxide (Eox), increases the short-circuit withstand time (SCWT), and reduces the switching energy loss. Channeling implantation was implemented to achieve a deep junction with low implantation energy in the proposed SG-MOSFET. The conventional MOSFET, conventional SG-MOSFET, and proposed SG-MOSFET were successfully fabricated and evaluated. The measured static, dynamic, and short-circuit characteristics were compared. In addition, 2D simulations were conducted to support the experimental results and extract the electric field in the gate oxide. The proposed SG-MOSFET outperforms the conventional SG-MOSFET with a 1.06× increase in BV and a 1.78× decrease in E ox . Additionally, the proposed SG-MOSFET shows a 1.52× improvement in SCWT compared to the conventional SG-MOSFET. Further, the proposed SG-MOSFET enhances [Ron × C rss ] by 2.66× in comparison to the conventional SG-MOSFET, leading to the reduction of E off and E total by 1.5× and 1.05×, respectively.
In SBD-embedded SiC MOSFETs, we attempted to improve the surge current capability while suppressing the bipolar operation that causes long-term reliability problems. By incorporating trigger p-n diodes that induce conductivity modulation, we expected that higher current could flow with a low voltage and the surge current capability would be improved. The effectiveness of the trigger diode was confirmed by preliminary TCAD simulation, and SBD-embedded SiC MOSFETs with trigger diodes were fabricated. By placing SBDs in the trigger diode region at the same intervals as in the cell region, maximum current density without bipolar operation was maintained. By distributing 3 to 4 adjacent trigger diodes over the entire chip, the conductivity modulation and heat generation were spread out over the entire chip, and the surge current capability was improved by 1.43 times compared with an SBD-embedded SiC MOSFET without trigger diodes.
The paper extends the investigation of the body diode (BD) turn-off process for 1.2 kV SiC MOSFETs [1]. Here, we investigate the devices under high current density (J=675 A/cm 2 ), fast switching (turn-on di/dt up to 6 A/ns) and high temperature conditions (T=175°C). The different aspects of body diode (BD) channel conduction, on-state carrier plasma and parasitic turn-on (PTO) are analysed in detail.
Ampere-class $\beta$ -Ga 2 O 3 trench heterojunction barrier Schottky diodes (THJBSs) were successfully developed for the first time. In fabrication, a lift-off process replacing an etching process was used to form $p$ -type Cu 2 O that works as a heterojunction component, which contributed to the realization of ampere-class devices. Experimental results with the fabricated $\beta$ -Ga 2 O 3 THJBSs indicate a turn-on voltage of 1.1 V, maximum current of 3.5 A, and specific on-resistance of $21 \mathrm{m}\Omega\cdot \text{cm}^{2}$ in forward characteristics. The breakdown voltage was −986 V with leakage current of $1.3\times 10^{-3}\ \mathrm{A}/\text{cm}^{2}$ in reverse characteristics. In double-pulse measurements, the devices exhibited fast and low-loss switching behavior similar to general Schottky barrier diodes (SBDs), suggesting that the device operated with only majority carriers. In addition, from a high-temperature reverse-bias (HTRB) test, steady reverse current without breakdown was confirmed under the stress for 428 h. These results confirm that the ampere-class $\beta$ -Ga 2 O 3 THJBSs are suitable for applications requiring fast switching, low loss, and high reliability.
In this work, a new 200V 0.18µm SOI-BCD platform has been developed comprehensively including the wide-SOA n&pLDMOS, low-Ron nLDMOS and LIGBT. It is noted that a ultra-thin N-drift has been skillfully applied below the shallow-trench-isolation (STI) structure for the low-Ron nLDMOS to realize an ultra-low specific on-state resistance (R on, sp ) with 20% decrease than the best reported study and the off-state breakdown voltage (BV off ) is also unsacrificed. Moreover, a linear buffer near the drain side has been arranged in the wide-SOA n&pLDMOS for high on-state breakdown voltage (BV on ). Finally, the reliability concerns have been also investigated fully including the negative bias temperature instability (NBTI) for the wide-SOA pLDMOS and hot carrier injection (HCI) for nLDMOS.
This paper presents an innovative architecture for gate-drivers, offering new solutions to short-circuit issues commonly faced by SiC MOSFET power transistors. Due to their fast switching, SiC power devices require much faster short-circuit detection times than those used for Si MOSFET and IGBTs. A gate driver IC with an integrated ultra-fast and accurate gate current sensor for short-circuit detection is presented. First experimental results demonstrates a low gate current copy error (<1%) with a response time that does not exceed 40ns and a reliable fast short-circuit detection for power modules, within 370ns. This IC is fabricated using NXP Semiconductors' high-voltage SMARTMOS10 130nm CMOS SOI technology.
Monolithic integration has been demonstrated to be an ideal solution to minimize the parasitics in GaN power IC. Nonetheless, the current commercially GaN process for power IC is far less mature and only n-type HEMTs are available. Therefore, it is difficult for high voltage level shifters to achieve high speed. This work implements a level shifter for GaN IC to achieve both small response time and high $\mathrm{d}V_{\mathrm{S}}/\text{dt}$ noise immunity without complicated signal processing circuits, thus delay and conduction loss will be minimized. The proposed circuit was fabricated in a $1\mu\mathrm{m}$ GaN-on-Silicon process and measured results were performed to verify the characteristics.
In this paper we present an integrated smart gate driver (SGD) capable of in-operation detection of SiC power MOSFET aging. The SGD IC monitors the discrete time differentiated (DTD) gate voltage slope, $\Delta V_{GS}$ , to identify the time to start of the Miller plateau, $t_{1}$ , during turn-on. Under known operating conditions, the value of $t_{1}$ can be used as an aging indicator to detect changes in the Miller plateau due to threshold voltage shifts. A synthesized digital central control unit (CCU) within the SGD can adjust the gate drive profile and gate drive bus voltage ( $V_{DR}$ ) based on the aging-induced changes in $t_{1}$ . We demonstrate that following 200 hours of high-temperature gate bias (HTGB) at 200 °C, $V_{DR, stress}=30\ \mathrm{V}$ , aging-induced gate degradation of a 1.2 kV 75A SiC MOSFET results in a decrease in drain current ( $I_{D}$ ) by 1.5%. An increase in $V_{\text{MP}}$ by 0.5 V can restore $I_{D}$ by 1.7% to pre-aged levels. This is achieved by adjusting the digital pulse width modulation (PWM) duty cycle of the on-chip DC-DC boost converter.
A low loss lateral insulated gate bipolar transistor (LIGBT) features an anode PNP structure and an integrated freewheeling diode (iFWD), named as PD LIGBT, is proposed and investigated by simulation. For the anode PNP structure, its P+ Collector shorts to the potential extracting contact above the P-top layer of iFWD, and its emitter is the anode of the LIGBT. During turning off period with the increasing $V_{\text{AK}}$ , the PNP is activated and hole current is allowed to flow through the PNP to iFWD. It suppresses the hole injection of the anode into the N-drift region, and thus the current density decreases quickly. Therefore, the PD LIGBT achieves a fast turning-off speed and reduces the $E_{\text{off}}$ significantly. In the on-state with low anode voltage $V_{\text{AK}}$ , the PNP is not activated, hence the PD LIGBT gets into bipolar conduction without snapback effect. Moreover, the iFWD can realize reverse conduction and obtain a low reverse recovery charge ( $Q_{\text{rr}}$ ). Compared with the SSA and STA LIGBTs, the proposed LIGBT reduces the $E_{\text{off}}$ by 81% and 70% at the same on-state voltage drop ( $V_{\text{on}}$ ), respectively. The reverse recovery charge of the proposed device is reduced by 49.5% compared with that of SSA LIGBT.
This article presents an alternative solution to the short circuit challenges commonly faced by ultra-fast power transistors. Specially 650V p-GaN HEMTs, where the short-circuit timing capability is very critical, and the presence of thermal run-aways is very sensitive. In response to this issue, a dedicated approach to detect the short-circuit inserting an on-line monitoring gate-resistor through a dual-channel segmented CMOS Gate Driver is proposed. The short-circuit indicator under Hard Switch Fault is based on the Gate-Schottky-Barrier leakage current, which is translated on a voltage drop at the gate-source voltage. The detection circuit can be fully integrated in the IC with a low monitoring voltage. A dual-buffer IC prototype including impedance state and monitoring integrated circuit using XFAB XT018 0.18um CMOS SOI technology was performed. Parametric results show a robust and quick detection propagation delay around 580ns under VDS = 400V and V GS = 5V.
In this work, a vertical $\beta$ -Ga 2 O 3 heterojunction barrier Schottky diode (HJBS) with hybrid unipolar and bipolar operation has been demonstrated by implementing p-type NiO. HJBS exhibits a low on-state voltage similar to the traditional Schottky barrier diode, and a low reverse leakage current close to NiO/ $\beta$ -Ga 2 O 3 heterojunction diode (HJD). The current conduction mode shifts from unipolar mode with high conduction resistance to bipolar mode with low conduction resistance when the forward voltage exceeds the turn-on voltage of the HJD. In addition, the hybrid operating mode of HJBS was further elaborated through temperature dependent electrical characteristics. These results preliminarily prove the existence of bipolar behavior in $\beta$ -Ga 2 O 3 HJBS.
This paper shows how the gate impedance $Z_{\text{gg}}$ characterization of a SiC-power MOSFET can be used to investigate its dielectric-semiconductor interface quality distinguishing the channel and JFET contributions. The $Z_{\text{gg}}$ characterization is performed for SiC power MOSFETs with SiO 2 and with high-k gate dielectrics. Different voltage- and temperature-dependencies of $Z_{\text{gg}}$ are identified in the respective SiC MOSFETs. The newer designs show an improvement with respect to the near semiconductor interface-traps. Experimental characterization and TCAD device simulations are carried out to support the conclusions.
This paper demonstrates a SiC lateral MOSFET (LMOS) with DOUBLE RESURFs (reduce surface field) technology to improve the device's breakdown voltage. The electrical characteristics and analysis of the fabricated SiC LMOS are carried out in terms of output, transfer and blocking characteristics, as well as the leakage current mechanisms. In particular, the effect of the length of the P-top RESURFs on device performance is studied. The experimental results indicate that the SiC LMOS with P-top RESURFs of length $7\ \mu\mathrm{m}$ exhibits best comprehensively with the highest breakdown voltage of 970 V, the highest Baliga's figure of merit BFOM of 83.6MW/cm 2 , and low (gate) leakage current. Which is recommended in this work and also encourages its further application in the power integrated circuits (Power ICs).
We propose a new high voltage MOS (HVMOS) structure and its gate control circuit for integrating a bootstrap diode (BSD) function into a 600V high voltage IC (HVIC). The new HVMOS structure is free from a parasitic PNP, and its drain drift resistance is lowered without sacrificing breakdown voltage. The new gate control circuit maintain the gate voltage of HVMOS high regardless of the frequency. The new 600V HVIC realizes a sufficient charging capacity even at a low frequency operation and a high tolerance of a VS negative surge.
AlN-based semiconductor devices are considered to outperform lateral AlGaN/GaN HFETs for power-electronic switching applications due to the high AlN-material breakdown field strength. We present an AlGaN/GaN /AlN-HFET transistor without any compensation doping in the AlN-buffer layer. Breakdown voltage scaling as function of the gate-drain separation of 140 V/µm and power figure-of-merit of 2.4 GW/cm 2 were achieved which is superior to most other GaN device technologies. 120 m Ω power transistors demonstrated 10 A switching transients up to 950 V off-state voltage and thus meet basic requirements for kW-range power switching. The origin of still present dispersion effects during high voltage switching could be attributed to a high structural defect density at the AlN-buffer / GaN channel material interface.
In the recent decade, the modern Smart Power Applications drive BCD technologies to higher voltage nodes (>100V), lower cost and isolation improvement. Thick SOI technology is one of the options providing sufficient breakdown and desired power. Doping of device wafer is setup low to support necessary spread of depletion region. Typical HV diode is made by implanting a layer of opposite dopant type. Lateral distance between anode and cathode contacts is then defining diode area and become more significant for higher operating voltage. Our work demonstrates a new approach that enable significantly smaller size without additional cost.
