This paper introduces an LC voltage controlled oscillator (VCO) in current-reuse configuration where transistors are biased in subthreshold region to save power consumption. A capacitive-feedback technique is employed to increase the output swing above the supply voltage and potential ground. Two capacitively source-degenerated negative resistors are employed to reduce the losses of the on-chip inductors resulting in an improved phase noise. The proposed VCO is designed and fabricated in 130nm CMOS technology. The overall circuit including core VCO and two buffers are biased at low supply voltage of 0.9V that consumes 490μW. The measured phase noise is − 110 dBc/Hz at 1MHz offset. A very high FOMT of − 199.3dBc/Hz has been achieved by including tuning range. The chip area is 0.6 × 0.8mm2.

This paper proposes 24GHz CMOS power amplifier (PA) for the short-range automotive collision avoidance radar.The proposed amplifier is implemented using TSMC 0.13µm RF CMOS technology with f T /f max of 120/140GHz.It is also powered by a 1.5V supply.The layout optimization technique is used to reduce total die size and parasitic capacitances.To improve power gain of the amplifier, the circuit has a 2-stage architecture and cascode scheme in the first stage.The proposed circuit showed the smallest chip size of 0.25mm 2 , the highest power gain of 29.3dB, the lowest power dissipation of 42mW, and the maximum PAE of 18.5% as compared to recently reported research results.

The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-mu m BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (g(m2)) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent HP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss (S-11) and output return loss (S-22) are kept below - 10 dB and -15 dB, respectively. The reverse isolation (S-12) is better than -50 dB.

This paper proposes a 24 GHz voltage-controlled oscillator (VCO) for the short range automotive collision avoidance radar. A low power and small area in fully-differential configuration has been proposed. The proposed circuit is implemented using TSMC 0.13 µm mixed signal/RF CMOS process, and it is powered by a 1.5 V supply. The overall circuit with core VCO and two buffers is biased at the low supply voltage of 0.9 V. The fabricated VCO showed very low power dissipation of 5.5 mW and tiny chip area of 0.0576 mm2 at the operation frequency of 24 GHz as compared to conventional research results.

This paper presents FPGA implementation for programmable digital FIR/IIR filter. Sine wave generation and detecting frequency of the sine wave signals have been proposed. Simulation results show that the system has the ability to provide a better frequency response for various cut-off frequencies. The design has been implemented in Altera, cyclone II family EP2C70F89618 device using Quartus software.

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS gm-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS–NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1–10.6 GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13 µm CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92 mW of dc power. The CMOS LNA features a maximum gain of 10.24 dB, 0.9–4.1 dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8 dBm at 6.3 GHz.

This paper presents a high gain and low power 24-GHz power amplifier (PA) for the short range automotive radar. The proposed circuit is implemented using TSMC 0.13-µm RF CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5-V supply. To improve power gain of the amplifier, it has a 2-stage cascode scheme. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF (radio frequency) are used to reduce parasitic capacitances at the band of 24 GHz. The proposed RF amplifier has low cost and low power dissipation since it is realized using all CMOS processes. The proposed circuit showed the smallest chip size of 0.12 mm 2 , the lowest power dissipation of 44.3 mW and the highest power gain of 24.04 dB as compared to recently reported research results.

This paper presents the design of a low-voltage and low-power frontend. It consists of a low noise amplifier (LNA) which integrates with mixer, and downconverts an 24-GHz RF input signal to an IF of 8-GHz. The first stage (LNA) uses complementary-push-pull configuration to save power consumption as well as to increase the trans-conductance and gain. A PMOS transistor is biased in the moderate inversion region functions as active load for LNA. It also converts the input voltage signal to current signal for the succeeding block which is a down-conversion mixer. The single-balanced mixer is accomplished to convert high frequency to intermediate frequency. The designed RF front-end uses the folded architecture to reduce the supply voltage and hence, power consumption. The whole circuit draws only 1.53 mA from 0.9-V power supply. The proposed circuit showed conversion gain of 12 dB and noise figure of 5.5 dB for -12dBm LO power.

In this paper, we present a new low-power Programmable Gain Amplifier (PGA) with a DC-offset cancellation to reduce chip area, cost and power. The PGA adjusts 8-level gains from 4dB to 60dB using the 8 CMOS switches and 16 passive resistors in parallel, and DC-offset circuit is based on a Miller effect technique. It is fabricated using Magnachip/SK Hynix 0.18-μm CMOS 1poly-6metal process. The proposed system showed excellent gain error of less than 0.24dB, very small die area of 0.015mm and low power consumption of 1.137mW.

A narrow band CMOS low noise amplifier (LNA) achieving high third-order input intercept point (IIP3) is proposed exploiting a non-linearity cancelation technique at RF frequency. In the modified derivative superposition (MDS) technique, one transistor is biased in the strong inversion region and the other is biased in the moderate inversion region instead of weak inversion region. A current-reused technique is employed to increase the trans-conductance (gm) of the amplifier and as well as the gain of LNA without increasing the power consumption. The linear LNA was designed and simulated in 0.13μm CMOS process. A gain of 14dB at 3.66GHz was exhibited and the simulated noise figure (NF) was 2dB. An IIP3 of 10.5dBm and a power consumption of 2.4mW from a 0.8V supply voltage were achieved. An input return loss (S11) of −10.6dB and an output return loss (S22) of −27dB were provided.

In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1–10.6GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push–pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13μm CMOS process. A gain of 19.5±1.5dB within the entire band was exhibited. The simulated noise figure (NF) was 1–3.9dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56dBm while consuming 4.1mW from a 0.6 power supply was achieved. The simulated input return loss (S11) was less than −5dB from 4.9 to 12.1GHz. The output return loss (S22) was below −10.6dB and S12 was better than −70.6dB.