This paper proposes a novel energy efficient authentic reliable routing protocol (EEARRP) to attain better authenticity in scalable mobile ad hoc networks. To decrease the signature verification expenditure and message communication expenditure a mechanism with message recovery is employed. The proposed authentic scheme is to minimize the size of the message transmitted when the signature length is reduced any more. To implement this, the energy efficient authentic reliable routing scheme with message recovery is used. Therefore, the communication overhead is minimized guaranteed in the above said scheme. The total length of the broadcast message is reduced by 24%. As a result, the total energy consumption of our scheme can be reduced by up to 27%. With the extensive simulation results using NS2 the proposed EEARRP attains better throughput, packet delivery ratio with reasonable decrease in total energy consumption and total overhead even in real-time scalable environment.

We describe light-weight protocols for selective packet ordering in out-of-order networks that carry memory traffic. The protocols are designed for heterogeneous high-performance systems, in particular, accelerated systems with end-points that have few resources available for interfacing the network. The protocols preserve the semantics of a relaxed memory ordering model as adopted by highly-threaded many-core processors and accelerators. The protocols achieve link-rate performance through the following techniques: (1) Speculative connection setup avoids round-trip delays found in protocols with little knowledge about endpoint resources, (2) target-side ordering avoids round-trip delays found in source-side ordering mechanisms, (3) fine-grained ordering removes dependencies unwarranted by program code avoiding cumulative ordering dependencies caused by coarse-grained ordering, (4) ordering relaxations and optimizations for producer/consumer communication patterns. We describe two ordering protocols that provide (1) strict sequential ordering and (2) relaxed ordering for multi-packet transfers. The protocols impose no restrictions on routing, including multipath routing.

Accelerators, such as GPUs, have proven to be highly successful in reducing execution time and power consumption of compute-intensive applications. Even though they are already used pervasively, they are typically supervised by general-purpose CPUs, which results in frequent control flow switches and data transfers as CPUs are handling all communication tasks. However, we observe that accelerators are recently being augmented with peer-to-peer communication capabilities that allow for autonomous traffic sourcing and sinking. While appropriate hardware support is becoming available, it seems that the right communication semantics are yet to be identified. Maintaining the semantics of existing communication models, such as the Message Passing Interface (MPI), seems problematic as they have been designed for the CPU's execution model, which inherently differs from such specialized processors. In this paper, we analyze the compatibility of traditional message passing with massively parallel Single Instruction Multiple Thread (SIMT) architectures, as represented by GPUs, and focus on the message matching problem. We begin with a fully MPI-compliant set of guarantees, including tag and source wildcards and message ordering. Based on an analysis of exascale proxy applications, we start relaxing these guarantees to adapt message passing to the GPU's execution model. We present suitable algorithms for message matching on GPUs that can yield matching rates of 60M and 500M matches/s, depending on the constraints that are being relaxed. We discuss our experiments and create an understanding of the mismatch of current message passing protocols and the architecture and execution model of SIMT processors.

During the last years cryptography has become both more powerful and popular. This paper will provide an overview of the RSA cryptosystem and elliptic curve cryptography, and it will also provide a comparison between the two. Although Elliptic Curve Cryptography (ECC) and RSA have several similarities in theory, one of them is much more complicated. On one hand the RSAs security depends on the diffilculty of integer factorization, as it is based on three famous theorems: Fermat’s Little Theorem, Euler’s Theorem and the Chinese Remainder Theorem. On the other hand ECCs security depends on the difficulty of solving ECDLP (or the Elliptic Curve Discrete Logarithm Problem). Because of the complexity of ECDLP, it seems that 1024-bit RSA and 160-bit ECC provides roughly the same security [1]. This means that ECC can provide the same security as RSA with shorter keys [2].

The Weighted Differential Scheduler (WDS) is a new scheduling discipline for accessing shared resources. The work described here was motivated by the need for a simple weighted scheduler for a network switch where multiple packet flows are competing for an output port. The scheme can be implemented with simple arithmetic logic and finite state machines. We are describing several versions of WDS that can merge two or more flows. An analysis reveals that WDS has lower jitter than any other weighted scheduler known to us.

We describe qHTFair, a switch scheduler that supports classes of service for networks on chips. The scheduler extends the HTFair scheduler, which is an improved version of the HyperTransport scheduling protocol. qHTFair is intended for on-chip interconnects with a daisy chain topology. With our extension, the interconnect can be divided into several classes or channels, each with its own bandwidth allocation. Bandwidth allocations are defined as ratios of channel bandwidths. Ratios can have arbitrary values and be set up dynamically.

NoCs have become a critical component in many-core architectures. Usually, the preferred topology is the 2D-Mesh as it enables a tile-based layout significantly reducing the design effort. However, new emerging challenges such as power consumption need to be addressed. Looking at the NoC, routers and links not being used must be switched off, thus achieving large power savings. Topology and routing algorithm must be carefully designed as they may lack enough flexibility to switch off components for long periods of time. We present the NR-Mesh (Nearest neighboR Mesh) topology. It gives an end node the choice to inject a message through different neighboring routers, thereby reducing hop count and saving latency. At the receiver side, a message may be delivered to the end node through different routers, thus reducing hop count further and increasing flexibility. When allowing links and routers to switch off and combined with adaptive routing, the power management technique is able to achieve significant power savings (up to 36% savings in static power consumed at routers). When compared with the 2D-Mesh, NR-Mesh reduces execution time by 23% and power consumption at routers by 47%.

In this paper, we present a flexible network on-chip topology: NR-Mesh (Nearest neighbor Mesh). The topology gives an end node the choice to inject a message through different neighboring routers, thereby reducing hop count and saving latency. At the receiver side, a message may be delivered to the end node through different routers, thus reducing hop count further and increasing flexibility when routing messages. This flexibility allows for maximizing network components to be in switch off mode, thus enabling power aware routing algorithms. Additional benefits are reduced congestion/contention levels in the network, support for efficient broadcast operations, savings in power consumption, and partial fault-tolerance. Our second contribution is a power management technique for the adaptive routing. This technique turns router ports and their attached links on and off depending on traffic conditions. The power management technique is able to achieve significant power savings when there is low traffic in the network. We further compare the new topology with the 2D-Mesh, using either deterministic or adaptive routing. When compared with the 2D-Mesh using deterministic routing, executing real applications in a full system simulation platform, the NR-Mesh topology using adaptive routing is able to obtain significant savings, 7% of reduction in execution time and 75% in energy consumption at the network on average for a 16-Node CMP System. Similar numbers are achieved for a 32-Node CMP system.

Capacitive coupled communication is a wireless chip to chip communication technology that uses capacitive coupling to transfer signals from a chip to neighboring chips. Its high-bandwidth, low-power, and low-latency chip-to-chip I/O capabilities enable the construction of high-performance and economical multi-chip modules (MCMs). Chips are placed face-to-face (Figure 1), with only a few microns of separation, such that overlapping transceiver circuits communicate through capacitive coupling between top-layer metal pads [1]. By using relatively small metal structures to communicate signals over short distances, capacitive coupled communication directly improves channel density, power, and latency to more closely match the performance of on-chip wires.

Many papers on emulations of Generalized Processor Sharing (GPS) have been published. The algorithms and their implementations are often very complex and/or generate a bursty output. In this paper, we present a simple two-priority scheduler that can be easily implemented in hardware, making it especially interesting for Networks on Chips (NoCs), and other applications dealing with stringent resource constraints.

To avoid head of line blocking in switches, Virtual Output Queues (VOQs) are commonly used. However, the number of VOQs grows quadratically with the number of ports, making this approach impractical for large switches. In this paper, we propose Dynamic Switch Buffer Management (DSBM) to tackle this problem. Similar to DBBM [3], it saves memory by reducing the number of buffers. Our scheme significantly improves the performance by dynamically assigning the incoming cells to the least occupied buffers.