We demonstrate a high speed GeSi electro-absorption (EA) modulator monolithically integrated on 3 µm silicon-on-insulator (SOI) waveguide. The demonstrated device has a compact active region of 1.0 × 55 μm(2), an insertion loss of 5 dB and an extinction ratio of 6 dB at wavelength of 1550 nm. The modulator has a broad operating wavelength range of 35 nm and a 3 dB bandwidth of 40.7 GHz at 2.8 V reverse bias. This compact and energy efficient modulator is a key building block for optical interconnection applications.

We demonstrate a compact waveguide-based high-speed Ge electro-absorption (EA) modulator integrated with a single mode 3 µm silicon-on-isolator (SOI) waveguide. The Ge EA modulator is based on a horizontally-oriented p-i-n structure butt-coupled with a deep-etched silicon waveguide, which transitions adiabatically to a shallow-etched single mode large core SOI waveguide. The demonstrated device has a compact active region of 1.0 × 45 µm(2), a total insertion loss of 2.5-5 dB and an extinction ratio of 4-7.5 dB over a wavelength range of 1610-1640 nm with -4V(pp) bias. The estimated Δα/α value is in the range of 2-3.3. The 3 dB bandwidth measurements show that the device is capable of operating at more than 30 GHz. Clear eye-diagram openings at 12.5 Gbps demonstrates large signal modulation at high transmission rate.

We present the design and fabrication of a waveguide-based Ge electro-absorption (EA) modulator integrated with a 3 µm silicon-on-isolator (SOI) waveguide. The proposed Ge EA modulator employs a butt-coupled horizontally-oriented p-i-n structure. The optical design achieves a low-loss transition from Ge to Si waveguides. The interaction between the optical mode of the waveguide and the bias induced electric field in the p-i-n structure was maximized to achieve high modulation efficiency. By balancing the trade-offs between the extinction ratio and the insertion loss of the device, an optimal working regime was identified. The measurement results from a fabricated device were used to verify the design. Under a -4Vpp reverse bias, the device demonstrates a total insertion loss (including the transition loss) of 2.7-5.2 dB and an extinction ratio of 4.9-8.2 dB over the wavelength range of 1610-1640 nm. Subtracting the contribution of the transition loss, the Δα/α value for the fabricated device was estimated to be between 2.2 and 3.2 with an electric field around 55 kV/cm.

We report a novel high-speed Ge photodetector on a large cross-section SOI waveguide platform. The device is butt-coupled with waveguide using a horizontal p-i-n junction configuration to enable highspeed operation. A very compact Ge detector with an active area of only 0.8 x 10 mu m(2), greater than 32GHz optical bandwidth at - 1V of reverse bias, and a responsivity of 1.1A/W is demonstrated. (C) 2010 Optical Society of America

We demonstrate a compact, high speed Ge photodetector efficiently butt-coupled with a large cross-section silicon-on-insulate (SOI) waveguide in which the Ge p-i-n junction is placed in the horizontal direction to enable very high speed operation. The demonstrated photodetector has an active area of only 0.8×10 μm2, greater than 32 GHz optical bandwidth, and a responsivity of 1.1 A/W at a wavelength of 1550 nm. Very importantly the device can readily be integrated with high performance wavelength-division-multiplexing filters based on large cross-section SOI waveguide to form monolithic integrated silicon photonics receivers for multichannel terabit data transmission applications.

We present a 90 nm test chip integrating proximity communication, optics using external lasers and photodiodes, and CML electronics on a single CMOS chip which can route data at multi-Gb/s rates through any combination of its three interconnect interfaces. A robust and flexible unclocked datapath allows independent timing and margin characterization of each path.

This article consists of a collection of slides from the author's conference presentation on multiterabit switch fabrics enabled by proximity communication. Some of the specific topics discussed include: future interconnect needs and requirements; data center trends; the concept of proximity communications; removing the chip input/output bottlenecks; system architectures to support interconnections; switch prototype characteristics; single-stage PxC switch advantages; system design considerations; scalable switch architecture; and future directions for proximity communication.