SSoft-switching inverters are essential for achieving high efficiency and low electromagnetic interference (EMI) in electric vehicle (EV) drive systems. However, designing filter inductors for such converters remains challenging. In sinusoidal triangular current mode (S-TCM)-based zero-voltage-switching (ZVS) inverters, the inductor is subjected to large triangular current ripple, intentional bidirectional current operation for ZVS, and variable switching frequency, making conventional fixed-frequency PWM inductor design approaches unsuitable. This paper presents a systematic design methodology for a high-power filter inductor specifically developed for S-TCM-based ZVS inverters. The proposed methodology combines analytical design calculations, experimental characterization of the magnetic material, and finite-element-method (FEM)-based electromagnetic and loss analysis. A 3C91 ferrite pot core and three winding configurations— Litz wire, copper foil, and solid copper wire—were investigated. The inductance of the designed inductors was validated experimentally and through FEMM and ANSYS simulations, while magnetic and winding losses were evaluated using FEM-based simulations in ANSYS. The core-loss coefficients of the 3C91 ferrite material were also experimentally determined for accurate loss estimation. Two parallel inductors per phase were employed to satisfy the required inductance and current-handling capability. The proposed methodology provides a practical framework for the systematic design and evaluation of high-power filter inductors by enabling accurate prediction of inductance, magnetic losses, winding losses, and thermal performance for S-TCM-based ZVS inverters used in EV powertrains and other high-frequency power conversion systems.

The thermal contact resistance between a clip-attached TO 247 package and heat sink is a very large contributor to the total thermal resistance. Therefore, it is important to investigate its reliability and lifetime behavior. The novelty of this investigation is the new, detailed lifetime behavior measurement results of thermal contact resistance between package and heat sink. We have carried out an accelerated lifetime test on 30 samples at 110 °C with acceleration factor of 35 for 18 weeks, corresponding to 12.1 years operating life in indoor environments. The samples were 7 without interlayer film, 12 with 12.5 µm thick silver film and 11 with 6 µm thick silver film. At the start of the test, the average of the thermal contact resistance of samples with 12.5 µm silver film was 20.7% lower, and with 6 µm silver film, the average of thermal contact resistance was 8.7% lower than the average of thermal contact resistance of samples without film. During the first operating month, thermal contact resistance decreased by an average of 5%. Then followed an additional 5% decrease for 12 years. All individual samples show lower thermal contact resistance after 12.1 years compared to the start. No failures were observed, not even among high outliers. By a visual inspection of heat sink surfaces, high outliers can be avoided from start. The thermal contact resistance variation is smaller for samples with silver films compared to samples without film. Samples show decreasing thermal contact resistance with increasing dissipated power. Several previously known stabilizing mechanisms can hypothetically explain the results. Not only the softness of silver, but also the high ductility and Poisson Ratio, which elongate a 12.5 µm thick film more than a 6 µm thick µm film, are hypothesized to better fill out microscopic voids. We observe silver film surface structure changes when comparing aged silver films to un-aged silver films, indicating material movements, but no exact mechanism could be proven. Therefore, the explanations studied are hypothetical. Since all measured thermal contact resistances were lower after 12.1 years, our conclusion is that stabilizing types of mechanisms are dominant during the operating lifetime for indoor environments.

This paper presents a calorimetric-based approach for non-invasive condition monitoring and reliability assessment of power semiconductor modules in electric vehicle traction inverters. The method quantifies conduction and switching losses by steady-state calorimetric measurements of the inverter cooling loop. All modules are mounted on a single cold plate; a single inlet and outlet temperature sensor and a flow meter measure coolant parameters to compute the total losses. Controlled DC excitation with both three-phase rotation and two-phase excitation sequences ensures near-uniform thermal exposure of all modules. By performing switching frequency sweeps, conduction and switching losses can be decoupled, and their evolution can be tracked over time. Observed trends provide insight into device degradation mechanisms, such as on-state resistance drift and variations in switching delays, enabling opportunities for future predictive maintenance and remaining useful life estimation.

This paper investigates the use of ON-state resistance ($R_{\text{dsON}}$) as a health monitoring indicator for diagnosing package-related degradation in silicon carbide (SiC) MOSFET devices. While $R_{\text{dsON}}$ is a widely recognized aging precursor, its application in SiC MOSFETs is challenging due to its strong dependence on junction temperature ($T_{\text{j}}$) and threshold voltage ($V_{\text{th}}$ drift during power cycling. To address these challenges, this work introduces compensation techniques that eliminate the influence of $T_{\text{j}}$ variations and $V_{\text{th}}$ drift in $R_{\text{dsON}}$. The proposed methods are validated through active power cycling tests on TO-247-3 packaged SiC MOSFETs, with experimental results showing that the compensated $R_{\text{dsON}}$ provides a stable and reliable health indicator. In addition, slope-based $V_{\text{th}}$ drift compensation methods, including moving average filtering and recursive least squares (RLS) estimation, are evaluated for detecting package-related degradation. Failure analysis using scanning acoustic microscopy (SAM) and scanning electron microscopy (SEM) confirms the correlation between compensated $R_{\text{dsON}}$ signatures and bond wire/solder degradation. The proposed method therefore enables reliable health monitoring of SiC MOSFET devices using $R_{\text{dsON}}$.

This article presents a novel bipolar field excitation system for pole-changing electrically excited synchronous machines. Conventional wireless power transfer (WPT)-based systems realize bipolar field current through receiver-side active converters and wireless gate-signal transmission, which increases complexity and reduces reliability. The proposed approach employs a dual-input, dual-output WPT system with anti-parallel outputs and a self-driven MOSFET-diode configuration, enabling bipolar current flow without rotor-side active converters or control signals. This simplifies the system, reduces control complexity, and enhances reliability. A small-scale proof-of-concept prototype has been experimentally validated, demonstrating bipolar current reversal up to 2.88A ( 118W ) with a self-driven rectifier efficiency of 99% under an inductive load emulating the field windings.

The electrification of heavy-duty vehicles (HDVs) is essential for achieving zero-emission freight transport. Conventional 400-800 V powertrains face limitations in supporting megawatt-level fast charging and high continuous power due to excessive current, cable losses, and thermal stress. Recent advances in high voltage (i.e., 1.7 kV, 2 kV, 3.3 kV) silicon-carbide (SiC) power modules and charging standards such as the Megawatt Charging System (MCS, up to 1250 V) have enabled a new generation of 1.2 kV dc-link architectures for HDVs. This paper presents a comprehensive system-level evaluation of increasing the dc-link voltage from 800 V to 1.2 kV, covering the battery, inverter, and motor subsystems. The battery/charging and motor-level results are presented as analytical first-order assessments, whereas the inverter-level loss-modelling methodology is experimentally validated on a 250 kW, 1.2 kV dc-link SiC prototype. A virtual-prototyping framework is used to quantify inverter losses, thermal behavior, and volume trade-offs, and the switching frequency is optimized by jointly considering inverter and motor harmonic losses. Experimental results show that the analytical models predict measured inverter losses within approximately 10% over the tested operating range. Under the representative charging assumptions adopted in this study, 1.2 kV dc-link voltage enables either an similar to 56% reduction in cable conduction losses or an similar to 33% reduction in cable mass, while the prototype achieves an efficiency of similar to 99.12%, a specific power density of 49.4 kW/L, and a bounding-box-based volumetric power density of 20.83 kW/L. The results provide system-level assessment and experimentally supported inverter-level design guidance for 1.2 kV HDV powertrains.

This study analyzes the sequential failure and remaining useful life (RUL) of a multi-chip power module (MCPM) using finite element (FE) simulation, an empirical lifetime model, and recursive deconvolution. The FE model captures electro-thermal interactions, while the empirical model estimates failure probabilities from power cycling test data. The deconvolution method refines the probability density function of the first failure, providing deeper insights into degradation trends. Results show that the first die in an MCPM can fail significantly earlier than the last, with temperature imbalances contributing to this variation. Despite early failures, the system can continue operating with minor thermal impacts. These findings highlight the need for adaptive failure management and improved thermal design to enhance reliability and system life time.

A power flow controller (PFC) may be needed to control the currents and power transmitted in the transmission lines in a highly meshed HVDC system. The paper presents a new and simple topology for series interline PFC for a simple 3 terminal HVDC system. Interline PFCs do not need an external power supply to change the current distribution in the HVDC system. The performance of the proposed PFC during steady state operation and ground faults is analyzed in detail using PLECS software. A protection circuit and its design aspects are also proposed for ground faults on one of the cables.

This paper presents an adaptive control scheme for cascaded H-bridge modular multilevel converters that reduces the voltage stress on selected components estimated to have degraded health. The proposed method independently controls the average voltage of each SM according to its estimated state of health. It is shown that the combination of the proposed control system and the virtual flux-based modulation results in minor changes in the quality of the output current while the converter operates with unequal submodule voltages.

Power flow controllers (PFCs) might be needed in highly meshed High-voltage direct current (HVDC) systems to redistribute the current and power in the various cables. This paper introduces two new unidirectional topologies, which are among the most simple PFC topologies. It describes the working principle, electrical characteristics, various fault cases, and the corresponding protection circuits in detail. Experiments have been conducted on a scaled-down prototype to verify the fullscale HVDC system simulations. Discussion and extension of the PFC with more than two transmission lines are provided.

This paper evaluates traction inverters for heavy-duty electric vehicles, focusing on key criteria such as raised power ratings with improved efficiency and power densities. Boosted voltage and current levels are required to achieve higher power levels and provide megawatt charging system solutions, which results in the need to utilize new semiconductors and topologies. In this study, 3-Level neutral point clamped (3L- NPC) and 2-Level 6-phase (2L-6Ph) voltage source inverters (VSIs) are evaluated and compared to conventional 2-Level 3-phase (2L-3Ph). The comparison uses figure-of-merit parameters and a virtual prototyping method based on several performance indices, such as efficiency, power density, output harmonic quality, and reliability. Then, efficiency maps are acquired to find out the sweet operating points, minimizing losses. Results show that the 3L-NPC VSI system provides a higher switching frequency, which also shrinks the size of the passive elements and cooling system. Although the 3L-NPC inverter requires additional power switches and isolated gate drivers, its estimated performance outweighs such reliability and cost-dependent issues. Therefore, this study concludes that multi-level inverter topologies hold promise for high-voltage, high-power traction drives.

This article presents a novel scheme for condition monitoring of dc-link capacitors in modular multilevel converters (MMCs). The proposed solution uses estimated capacitance values of the dc-link capacitors for indicating their state-of-health (SoH). Moreover, a comparative approach is proposed, where the estimated capacitances of all submodule capacitors are used to separate parameter drifts caused by aging from parameter drifts caused by other factors such as temperature change. It is shown in simulation and experimental results that an equal drift in all capacitance estimates can be a result of factors other than aging. However, a drift in the capacitance of one capacitor compared to the average capacitance of all submodules may be attributed to aging of that specific unit. Using the proposed comparative technique, there is no need for additional temperature sensors to account for the effect of temperature variations on the online estimations. Simulation and experimental results demonstrate an overall estimation error of less than 1% when applying the proposed comparative technique.

Double-sided cooled (DSC) power semiconductor modules have garnered increased interest over the past decade due to their ability to offer an additional path for heat removal, facilitating higher power density operation while reducing junction temperatures and thermal stresses. Nevertheless, when operating at similar junction temperatures, DSC modules might exhibit elevated thermo-mechanical stress compared to single-sided cooled (SSC) modules. This increase can be attributed to restricted vertical movement within the DSC modules. Furthermore, the integration of various spacers within the DSC modules, which enable bond wire connections to gate terminals, can significantly influence both the thermal performance and induced thermo-mechanical stresses. Depending on the materials used in the spacer, the thermal performance and thermo-mechanical stresses inside the module can vary. In this study, we have first analysed the thermal performance of the DSC power modules employing different spacers. Following that, we have also performed thermo-mechanical analysis in different solder layers. Finally, fatigue analysis is done to demonstrate the weakest solder layer inside the package.

The demand for highly efficient and dynamic electric vehicles (EVs) has increased dramatically. The traction inverter, a pivotal component in an EV powertrain, plays a crucial role. This study is dedicated to designing a traction inverter with focus on achieving high efficiency and elevated power density and mitigating electromagnetic interference (EMI) issues. To realize these objectives, autonomous gate drivers (AGDs) are proposed and designed using LTspice simulation software. The aim is to achieve zero voltage switching (ZVS) at both turn-on and turn-off through the utilization of triangular current mode (TCM) control on the gate driver. The AGDs implement a current modulation scheme by sensing the current and voltage and generating gate-source voltage signals with minimal delays. The implemented current modulation scheme by the AGDs results in an efficiency exceeding 99% for a 10 kW power rating. The sinusoidal output waveforms not only contribute to extending the motor lifespan by mitigating sharp-edge voltages but also bring advantages such as reduced switch stress, decreased EMI, and simplified thermal management.

The semiconductor industry plays a critical role in numerous sectors, yet faces vulnerability in its supply chains. The recent global semiconductor shortage highlighted the risks of relying on a single supplier. To mitigate this, companies adopt dualsourcing strategies, but power devices like silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) pose challenges due to manufacturing nuances. Configurable gate-drive units (GDUs) offer flexibility but often require external input for device recognition. This paper introduces a method to achieve a self-configurable gate-drive unit based on measuring the gate step-response for power device identification. The proposed method enhances safety, ensures seamless integration, and offers adaptability in full-bridge or multi-phase systems. Experimental results demonstrate component uniformity, emphasize the importance of interval selection, and showcase the impact of external gate resistors on rise and fall times. Estimations of input capacitance using different methods highlight their effectiveness in distinguishing among devices. The practical implementation of the proposed method contributes to the efficiency, reliability, and cost-effectiveness of self-configurable GDUs.

The fault clearance time in the power system can vary from a few milliseconds to a few hundred milliseconds. Power electronics converters should be able to provide the increased current during faults without failing due to thermal limits. Hence, the heat generated in the semiconductor chip due to the over-current (OC) should be removed as soon as it is generated. In this paper, cooling by heat-absorbing material has been investigated on the top, bottom, and top $+$ bottom of the SiC MOSFET chip using COMSOL simulations for OCs. The heat-absorbing materials considered in the paper are copper, graphite, and aluminum. The maximum allowed chip temperature is assumed to be 250 ˆC since SiC devices do not fail in this range of temperature. It is concluded that the cooling on the top of the chip has the best performance among the three arrangements discussed in the paper in terms of OC duration and steady-state temperature. Another conclusion is that copper has the best performance due to higher thermal capacity for the same volume of the heat-absorbing material.

Gate oxide degradation under dynamic gate stress has been demonstrated as a reliability issue for SiC MOSFETs recently. Investigating the influence of dynamic drain-source voltage stress ( VDS ) and load current ( IL ) involved in switching operation on gate oxide degradation is very significant to identify the way for effectively assessing gate oxide reliability. In this article, a buck converter with continuous switching condition and constant high temperature is built and operated to evaluate gate oxide degradation. Moreover, the results from buck converter are compared to results regarding AC bias temperature instability (BTI) under the same conditions for devices with different gate structures. The degradation degree of different gate oxide locations under the two operations is analyzed combining I-V and split C-V characteristics. It is found that there is consistent degradation of the gate oxide above JFET region, but depending on the operation mode, the degradation is different above channel region, indicating that VDS and IL have different effects on different gate oxide locations. Therefore, AC BTI test cannot sufficiently evaluate gate oxide degradation and may overestimate or underestimate its reliability, depending on the device structure and fabrication process. It is necessary to investigate the gate oxide reliability in typical switching operation.

In this paper, a novel approach for condition monitoring of dc-link capacitors in modular multilevel converters (MMCs) is proposed. The solution is intended for flexible alternating current transmission systems (FACTS) and high voltage direct current (HVDC) applications. The proposed technique does not require any current measurements and solely relies on voltage measurements that are already available in MMCs. The independence from current measurements simplifies the estimation process and reduces the uncertainties that may arise from current sensors. Experimental results demonstrate an overall estimation error of less than 1% when applying the proposed technique, which is similar to the error produced by methods that use current measurements for condition monitoring.

Grid-forming converters can emulate the behavior of a synchronous generator through frequency droop control. The stability of grid-forming modular multilevel converters can be studied via the impedance-based stability criterion. This paper presents an ac-side impedance model of a grid-forming modular multilevel converter which includes a complete grid-forming control structure. The impact of different control schemes and parameters on the closed-loop output impedance of the converter is thoroughly analyzed and the learnings have been used in mitigating undesired control interactions with the grid. The results are verified through simulations in time- and frequency-domains along with experiments on a down-scaled laboratory prototype.

This study compares shunt-based and SiC MOSFET R ds(on) -based autonomous gate drivers (AGDs) for triangular current mode (TCM)-based zero voltage switching (ZVS) two-level three-phase inverters for electric vehicle (EV) drive systems. Integrating ZVS and TCM control techniques significantly reduces switching losses, enhances overall system efficiency, and mitigates electromagnetic interference (EMI) issues. The AGDs, based on a current modulation scheme, sense switch voltage for turn-on at ZVS and switch current for turn-off, using either a shunt or SiC MOSFET R ds(on) . When the switch current exceeds a predefined value, the AGD facilitates ZVS turn-off with external snubber capacitance. Performance evaluation includes gate-source voltage generation, optimum blanking time, ZVS turn-on/off, and efficiency supported by simulation results. The discussion covers the advantages, limitations, and impact of the proposed inverter design on EVs, providing valuable insights for the selection and implementation of AGDs in EV drive systems.