Baseband functions like channel estimation and symbol detection of sophisticated telecommunications systems require matrix operations, which apply highly nonlinear operations like division or square root. In this paper, a scalable low-complexity approximation method of the inverse square root is developed and applied in Cholesky and QR decompositions. Computation is derived by exploiting the binary representation of the fixedpoint numbers and by substituting the highly nonlinear inverse square root operation with a more implementation appropriate function. Low complexity is obtained since the proposed method does not use large multipliers or look-up tables (LUT). Due to the scalability, the approximation accuracy can be adjusted according to the targeted application. The method is applied also as an accelerating unit of an application-specific instruction-set processor (ASIP) and as a software routine of a conventional DSP. As a result, the method can accelerate any fixed-point system where cost-efficiency and low power consumption are of high importance, and coarse approximation of inverse square root operation is required.

In this paper, a new Minimum Description Length (MDL) approach for the characterization of a mobile phone's color camera is presented. The use of high-order polynomials, Fourier sine series, and artificial neural networks (ANN) for solving this problem are compared and contrasted. The MDL formalism is used for determining the stochastic complexity of polynomial and Fourier sine models for the characterization of a Nokia N93 mobile phone camera. A quantitative evaluation of their performances, as well as for using an ANN, is provided.

Our topic is reciprocal and reciprocal square root and we propose processing element without iterations. Implementation is based on look-up tables and computation in logarithm domain. Simulation results and implementation complexity for 16 bits input operand with fixed point and floating point output formants are presented. Two truncation methods, LSB and half LSB, for output are presented and their impact to output error is discussed. Relative error for reciprocal is less than 5% for floating point output format.

The number of wireless Internet users is expected to increase rapidly within the next few years resulting in a huge increase in the number of bits transferred between wireless devices and networks. When looking at current mobile networks, they have mainly been designed for optimized delivery of voice calls and not for broadband data. Although mobile networks are evolving, we expect there to be a need for complementary solutions for providing wireless Internet access. Thus we introduce an ad-hoc networking solution using WiFi short range radio technology for extending cellular wireless broadband coverage and capacity into places where it is most urgently needed; densely populated areas and indoors. We further propose connecting the ad-hoc networking solution to the operator's total access offering. As a result, wireless users may enjoy an easy to use, good quality, secure and robust service offering when entering the wireless Internet era, and access providers are equipped with tools to utilize complementary access technologies in places where they suit best. Operators arc able to make efficient use of their existing investments and open new service concepts and business models with mobile Internet domain use cases evolution. Also end users become an essential part of business ecosystem by providing content, services and access to other users.

Fixed-point simulation results are used for the performance measure of inverting matrices by Cholesky decomposition. The fixed-point Cholesky decomposition algorithm is implemented using a fixed-point reconfigurable processing element. The reconfigurable processing element provides all mathematical operations required by Cholesky decomposition. The fixed-point word length analysis is based on simulations using different condition numbers and different matrix sizes. Simulation results show that 16 bits word length gives sufficient performance for small matrices with low condition number. Larger matrices and higher condition numbers require more dynamic range for a fixedpoint implementation. Keywords—Cholesky Decomposition, Fixed-point, Matrix inversion, Reconfigurable processing.

This paper considers the implementation of multi-user detector in MC-CDMA receivers using fixed-point matrix inversion algorithms. The fixed-point word length analysis is based on the matrix condition number analysis and residual errors. The obtained bit error results have been compared to floating point matrix inversion results.

Both the matrix inversion and solving a set of linear equations can be computed with the aid of the Cholesky decomposition. In this paper, the Cholesky decomposition is mapped to the typical resources of digital signal processors (DSP) and our implementation applies a novel way of computing the fixed-point inverse square root function. The presented principles result in savings in the number of clock cycles. As a result, the Cholesky decomposition can be incorporated in applications such as 3G channel estimator where short execution time is crucial

Matrix inversion is a general problem in a wide variety of applications. The problem becomes even more challenging when an efficient hardware implementation is required. In this paper, three matrix inversion implementations in fixed-point are presented and compared. The fixed-point implementation of such methods is considered and the needed processing elements are introduced. The characteristics of each approach are described and their hardware implementations are compared.

Fixed-point simulation results are used for the performance measure of inverting matrices by Cholesky decomposition. The fixed-point Cholesky decomposition algorithm is implemented using a fixed-point reconfigurable processing element. The reconfigurable processing element provides all mathematical operations required by Cholesky decomposition. The fixed-point word length analysis is based on simulations using different condition numbers and different matrix sizes. Simulation results show that 16 bits word length gives sufficient performance for small matrices with low condition number. Larger matrices and higher condition numbers require more dynamic range for a fixedpoint implementation. Keywords—Cholesky Decomposition, Fixed-point, Matrix inversion, Reconfigurable processing.

This paper presents a fixed-point matrix inversion implementation of a linear minimum mean square error (LMMSE) channel estimator for GSM receivers. The matrix inversion algorithm uses Cholesky decomposition implemented by a reconfigurable processing element. The fixed-point word length analysis is based on the bit error rate (BER) simulations using standard GSM channel models: TU, HT, and RA. The obtained results are compared to floating point matrix inversion results. Our simulations show that 16 bits fixed-point implementation of matrix inversion in LMMSE estimator gives equal BER performance compared to floating point matrix inversion. The condition number of involved matrices in LMMSE estimator varies depending on the channel model. This variation affects the word length requirements of the matrix inversion engine.

Reference design for radio part is OKI’s ML7050LA [2] single chip RF having for example following blocks integrated: Low noise amplifier (LNA), power amplifier (PA), image rejection mixer (IMR). Block diagram of ML7050LA is in Figure 1. By assuming to use 3 V supply voltage Tx power dissipation is 102mW and Rx power dissipation is 165mW. Abstract—Wireless sensor networks have several challenges and one of those challenges is power efficiency. Almost in all cases in wireless sensor network’s nodes get their energy from batteries without having capability for charging. One design constraint is long operating time so efficient energy management in all levels play key role. This paper briefly introduces power management concept in different design levels – VLSI design techniques for low power designs, energy efficient protocols and energy efficient topologies.

This paper proposes a coarse grain reconfigurable processing element (PE) for future telecommunication equipment. The authors described the first release of the simple processing element architecture that is capable to basic arithmetic operations such as addition, subtraction, multiplication, division, square and square root with same hardware (HW) processing element. It also can provide base of 2 logarithms. The proposed architecture guarantees predefined throughput and clock frequency for all these arithmetic operations