Technological advances and social transformations have enabled the circulation of a large amount of data in the health area. Analyzing this data becomes more critical and more challenging as the volume of data increases. An alternative to performing this analysis is to use data analysis techniques to process input data sets and build consistent databases for input to machine learning algorithms. Thus, it can forecast future scenarios and collaborate with knowledge discovery. In this context, this work aims to develop a parameterizable system with automated decisions capable of collecting and analyzing many indicators provided by the World Health Organization (WHO). After these analysis steps, the system applies machine learning algorithms for predictions of different indicators to process information automatically, finding different knowledge discovery scenarios. Thus, the contribution of this article is an automated and intelligent system for WHO data forecasting. The efficiency of the system's choices and forecasts was proven with experiments in five different areas of health, obtaining assertiveness by up to 99.92%, root-mean-square error (RMSE) by up to 0.0286, and Kling-Gupta Efficiency (KGE) by up to 0.9988, hitting even the most complex cases, as shown in the confusion matrices. Finally, three case studies were carried out to expand the studies and present the potential of the system in different contexts: anemia in children, age-standardized suicide rates in men, and number of road traffic deaths.

Machine Learning applications have their viability strongly linked to the ability of computer architectures to offer high performance and energy efficiency. Although different architectures can offer high computational performance, they may lack energy efficiency, which is crucial for consumer-based applications. For instance, Intrusion Detection Systems can use Machine Learning techniques to monitor network traffic and identify possible malicious activities. These systems are constantly active on devices such as firewalls, reinforcing the need for energy efficiency, e.g., in smart homes and autonomous vehicles. Field-Programmable Gate Array (FPGA) can offer better energy efficiency than other architectures. Considering that, we designed and evaluated a CPU+FPGA-based Convolutional Neural Network for Intrusion Detection Systems. We deployed our strategy in a heterogeneous CPU (Intel Xeon) + FPGA (Arria 10) platform. Then, we compared the proposed architecture with its respective parallel software version for power, energy, and performance evaluation. The NSL-KDD data set was used for intrusion detection benchmarking. The energy efficiency results for CNN showed up to 4.5× more operations per watt than its software version.

High-performance computing (HPC) systems need to handle ever-increasing data sizes for fast processing and quick response times. However, modern processors’ caches are unable to handle massive amounts of data, leading to significant cache miss penalties that affect performance. In this context, selecting an effective cache replacement policy is crucial to improving HPC performance. Existing cache replacement policies fall short of Bélády’s optimal algorithm, and we propose a new approach that leverages the coherence state and sharers’ bit-vector of a cache block to make better decisions. We suggest a reinforcement learning-based strategy that learns from past eviction decisions and applies this knowledge to make better decisions in the future. Our approach uses a next-attempt method that combines the results from classic cache replacement algorithms with reinforcement learning. We evaluated our approach using the Sniper simulator and seven kernels from CAP Benchmarks. Our results show that our approach can significantly reduce the cache miss rate by 41.20% and 27.30% in L1 and L2 caches, respectively. In addition, our approach can improve the IPC by 27.33% in the best case and reduce energy consumption by 20.36% compared to an unmodified policy.

Uma das criações mais impactantes na área de processadores foi o conceito de pipeline superescalar, cujo objetivo era minimizar gargalos e atender demandas dos seus usuários, garantindo aumento de instruções por ciclo. Porém, como trade-off, trouxe maior complexidade à arquitetura e necessidade de maior controle sobre dependências de instruções. Para solucionar essa problemática, Robert Tomasulo idealizou um algoritmo que é utilizado até os dias de hoje. No artigo em questão, é apresentado um simulador em linguagem C do algoritmo de Tomasulo com o conjunto de instruções RISC-V, que demonstra o passo a passo das estruturas idealizadas por Tomasulo, a análise de dependências entre instruções e suporte à instruções de desvio.

: Formal Concept Analysis (FCA) usage for information extraction has been increasingly recurrent, using algorithms already developed for this purpose. However, the computational effort involved in analyzing and extracting information can drastically increase in the case of dense and high-dimensionality databases. The main goal of this work is to present a parallel approach to solving this problem. We propose parallelizing In-Close 4 with C++ and OpenMP to generate formal concepts in multiple threads. Our approach is based on the subdivision of formal contexts into subcontexts grouped by a single set of objects. In addition, we propose a set of operations to obtain the original formal concepts from the quasi-concepts, concepts generated from the subcontexts. Our results show a speedup of up to 1.4116x with an efficiency of 70.48% for 100,000 objects, 50 attributes, and a density of 50%.

A evolução das tecnologias exige cada vez mais poder de processamento dos computadores (e.g., smartphones, tablets, notebooks, desktops e servidores), sendo demandado desempenho e eficiência. Um dos principais componentes associados ao desempenho de um computador é a memória e, portanto, o quão rápido um dado ou instrução pode ser acessado pelo processador. Durante a graduação em Ciência da Computação, os estudantes estão imersos a diversas disciplinas capazes de trazer compreensão da importância da memória. No entanto, uma delas por objetivo, trata a hierarquia de memória com destaque: Arquitetura de Computadores. Em linhas gerais, aprender os efeitos positivos e negativos de uma exploração de memória está no entendimento de como explorar a localidade espacial e temporal de forma a reduzir os impactos em cache miss e page fault. Por este motivo, este artigo apresenta como objetivo principal um estudo e abordagem de aprendizado de hierarquia de memória usando o simulador Amnesia. Esta abordagem tem sido utilizada na disciplina de Arquitetura de Computadores III. Entre os resultados alcançados está este artigo, que em sua versão inicial, foi elaborado como um dos produtos do trabalho da disciplina. Como contribuição, está a abordagem de aprendizado e o amadurecimento dos estudantes envolvidos no trabalho.

Lightweight manycore processors deliver high performance and energy efficiency by bundling hundreds of low-power cores, a distributed memory architecture with small local memories and Networks-on-Chip in a single die. However, the lack of rich and portable programming models for these processors makes software development a challenging task. Currently, two approaches are employed to address programmability in lightweight manycores: Operating Systems (OSes) and baremetal runtime libraries. The former provides portability but exposes complex Operating System (OS)-level programming interfaces to developers. The latter focuses on providing rich and high performance interfaces, which are vendor-specific and yield to non-portable software. In this work, we address these programmability and portability challenges by combining a rich OS with a well-known standard for parallel programming. We propose a portable and lightweight Message Passing Interface (MPI) library (LWMPI) designed from scratch to cope with restrictions and intricacies of lightweight manycores. We integrated LWMPI into Nanvix, an open-source distributed OS that runs on silicon lightweight manycores. The results obtained with a synthetic benchmark and a subset of the CAP Bench applications running on Kalray MPPA-256 unveil that LWMPI not only delivers a lightweight and richer programming interface but also presents good performance and scalability results.

Sistemas operacionais são desenvolvidos com o intuito de possuir a melhor otimização e funcionamento para diversas arquiteturas de processadores. A implementação é um processo delicado, já que diversas tecnologias diferentes emergem constantemente. Neste trabalho, é apresentado o desenvolvimento do port do sistema operacional Nanvix para uma arquitetura RISC-V, que vai ser emulada a partir de uma ferramenta denominada PULP SDK. Para verificar o funcionamento do port, testes automatizados foram realizados, desde o nível de kernel ao de usuário.

During two years of COVID-19 lockdown for Brazilian universities, new online teaching techniques showed us that the main problem with education is learning. If we compare the methods from one hundred years ago and now, we changed technologies, but we kept the same method to learn because we are humans, i.e., we need to socialize. It is necessary to understand reactions, live, and learn together in the same space, real or not. A disruptive approach to learning will likely be based on something other than a metaverse, but on a download to the brain, and it does not exist yet. However, how is this discussion related to computer architecture? Although we understand the concern about education methods and how wide it is, computer architecture is one of the bases of computer science and engineering. New methods that remove socialization in this new postlockdown educational environment can also partially remove the bases for a good computer scientist or engineer. Despite that, we can try a hybrid approach, and this report paper intents to present a post-lockdown experience about teaching and learning in a computer architecture class.

Lightweight manycore processors deliver high performance and scalability by bundling in a single chip hundreds of low-power cores, a distributed memory architecture and Networks-on-Chip (NoCs). Operating Systems (OSes) for these processors feature a distributed design, in which a communication layer enables kernels to exchange information and interoperate. Currently, this communication infrastructure is based on mailboxes, which enable fixed-size message exchanges with low latency. However, this solution is suboptimal because it can neither fully exploit the NoC nor efficiently handle the diversity of OS communication protocols. We propose an Inter-Kernel Communication (IKC) facility that exposes two kernel-level communication abstractions in addition to mailboxes: syncs, for enabling a process to signal and unlock another process remotely, and portals, for handling dense data transfers with high bandwidth. We implemented the proposed facility in Nanvix, the only open-source distributed OS that runs on a baremetal lightweight manycore, and we evaluated our solution on a 288-core processor (Kalray MPPA-256). Our results showed that our IKC facility achieves up to 16.87× and 1.68× better performance than a mailbox-only solution, in synchronization and dense data transfers, respectively.

O uso de programação paralela torna-se cada vez mais essencial, bem como o uso de ferramentas que auxiliam o programador nas tarefas de paralelismo e obtenção do melhor desempenho da arquitetura utilizada. Assim, o objetivo deste trabalho é a criação de uma otimização de paralelização de código em C/C++ que utiliza Aprendizagem por Reforço para realizar a paralelização automática de código em GPU utilizando a linguagem CUDA. Os experimentos realizados mostraram que a otimização criada é capaz de realizar a paralelização automática em CUDA, conseguindo altos speedups.

Acute Respiratory Tract Infections are among the leading causes of child mortality worldwide. Specifically, community-acquired pneumonia has different causes, such as: passive smoking, air pollution, poor hygiene, cardiac insufficiency, oropharyngeal colonization, nutritional deficiency, immunosuppression, and environmental, economic and social factors. Due to the variation of these causes, knowledge discovery in this area of health has been a great challenge for researchers. Thus, this paper presents the steps for the construction of a database and evaluation results applied to the analysis and prediction of potential deaths caused by childhood pneumonia using the Pictorea method. For this, the Random Forest and Artificial Neural Network algorithms were used, and after comparison, the Neural Network algorithm showed higher accuracy by up to 87.57%. This algorithm was used to analyze and predict the number of deaths from pneumonia in children up to 5 years old, and the results were presented using Root Mean Square Error and scatter plots. A domain specialist validated the results and defined that the pattern found is relevant for future studies in the medical field, helping to analyze the behavior of countries and predict future scenarios.

Multikernel operating systems (OSs) were introduced to cope with challenges in software development and deployment in lightweight manycores. Among the possible structures for a multikernel OS, we focus on designs based on asymmetric kernels. This design delivers better performance isolation, but it suffers from an overhead in energy efficiency. In this letter, we overcome this issue with a co-design solution between the cluster of a lightweight manycore and an asymmetric kernel. We designed a 4-core heterogeneous cluster with one core tuned for the OS kernel and we patched the OS kernel to better match the characteristics of this core. Our experiments unveiled that our solution consumes 14.1% less power than the baseline and also improves the OS kernel performance by up to 6.5%.

Algorithms for the extraction of formal concepts are widely studied in several areas of knowledge, such as finance, health, and statistics. However, these algorithms require high‐performance processing due to their combinatorial characteristics. In this work, an Open computing language (OpenCL)‐based Brute Force algorithm is proposed and evaluated for formal concept extraction on heterogeneous architectures (CPU+GPU and CPU+FPGA). The CPU+GPU architecture presents higher performance and scalability than other architectures when our Brute Force algorithm processes high dimensional contexts with many objects and attributes. Our parallel approach shows performance results up to 18× better than a smarter sequential algorithm called Data‐Peeler. Moreover, our Brute Force algorithm running on CPU+GPU architecture has greater energy efficiency, reaching at least 1.79× more operations per energy consumption than other algorithms on different architectures explored in this work.

Mobile devices have become indispensable to communication over the last decade. In a hypothetical scenario in which conventional forms of connection such as antennas and satellites are not available, other forms of information propagation must be used. Ad-hoc broadcasts are strategies for maintaining communication between devices in these situations, however, they require high transmission power. This article proposes the use of priority queues, such as the Fibonacci heap and the binary heap in the Dijkstra algorithm, in order to reduce its computational cost in the search for the smallest network route. From the limitation of the signal strength to reach the nearest device, our results obtained lower transmission power compared to the standard device settings. Simulations show that a fibonacci heap has higher performance than binary heap in networks with higher number of connections. This way, the implementation of the fibonacci heap brings improvements in the computational cost of the algorithm. In addition, we show that the calculation of the smallest route is directly connected to the choice of the path with the lowest transmission power.

The fight against crime in Brazilian cities is an extremely important issue and has become a priority agenda in public, statutory or municipal discussions. Even so, reducing cases of violence is a complex task in large Brazilian cities, such as Rio de Janeiro and Sao Paulo, as these large cities have vast criminal points. Therefore, this paper presents the steps followed in the process of knowledge discovery applied to prediction of crime rate numbers in different regions of Sao Paulo city in order to better understand it and distribute the security forces more efficiently. Then, a hybrid model composed of an Artificial Neural Network and the SARIMA mathematical model was applied to databases related to different areas of the city. The average results showed assertiveness rates of 83.12% and 76.78% and root mean square deviation of 1.75 and 2.16 for two different tests.

The performance and energy efficiency provided by lightweight manycores is undeniable. However, the lack of rich and portable support for these processors makes software development challenging. To address this problem, we propose a portable and lightweight MPI library (LWMPI) designed from scratch to cope with restrictions and intricacies of lightweight manycores. We integrated LWMPI into a distributed OS that targets these processors and evaluated it on the Kalray MPPA-256 processor. Results obtained with three applications from a representative benchmark suite unveiled that LWMPI achieves similar performance scalability in comparison with the low-level vendor-specific API narrowed for MPPA-256, while exposing a richer programming interface.

Ambientes de desenvolvimento para lightweight manycores pecam em prover uma boa relação entre programabilidade e portabilidade. Neste contexto, este artigo propõe mecanismos de comunicação entre clusters para um sistema operacional distribuído que sejam precisos, fáceis de usar, escalonáveis e facilmente portáveis. Os resultados mostram ser possível suportar algoritmos de comunicação colectiva de forma eficientemente.

Over the years, the amount of data shared between users from different areas have grown considerably. Consequently, so did network attacks. Security monitoring strategies must classify information types on networks quickly and effectively. Intrusion Detection Systems have been proposed with Machine Learning techniques and High-Performance Computing to avoid security anomalies. Thus, FPGA devices are good candidates to improve performance and energy efficiency. In this brief, we propose a reconfigurable FPGA-based K-means/K-modes architecture to accelerate the data clustering for network intrusion detection. We evaluated our approach over NSL-KDD data set and the results showed that K-means and K-modes can achieve up to 15× and 994× more operations per Watt than parallel software versions.

In today's SOC, the number of processing cores is increasing with growth of VLSI technology. The on chip communication among multiple cores using NOC based architecture is effective than conventional bus based architecture, Since NOC has many advantages than bus based architecture mainly in terms of scalability (increase in number of nodes) and flexibility. Hence in this paper, Mesh based NOC architecture with packet switching is adopted for cryptography without virtual channel and pipelining techniques. The deterministic X-Y routing algorithm is used for routing a packet within the NOC. This paper presents a 10 -20% less area consumption NOC with AES as processing element , over previous work.